Having followed GF since its inception, I agree with CTO Gary Patton, what we are seeing today truly is a different GLOBALFOUNDRIES! Our first GF blog was published on 9/13/2009 and we have done a total of 173 GF related blogs that have collected more than 1.5M views thus far. 72 of those blogs were written by me so I have followed this… Read More





Intrinsix Fields Ultra-Low Power Security IP for the IoT Market
As the Internet-of-Things (IoT) market continues to grow, the industry is coming to grips with the need to secure their IoT systems across the entire spectrum of IoT devices (edge, gateway, and cloud). One need only look back to the 2016 distributed denial-of-service (DDoS) attacks that caused internet outages for major portions… Read More
Clock Gating Optimization
You can save a lot of power in a design by gating clocks. For much of the time in a complex multi-function design, many (often most) of the clocks are toggling registers whose input values aren’t changing. Which means that those toggles are changing nothing functionally yet they are still burning power. Why not turn off those clock… Read More
IoT SoCs Demand Good Data Management and Design Collaboration
Design data management has always been important. Board designers have known this for decades as they had to have ways to keep all their discreet components organized and understood. Sourcing components is not easy as it means hours of reading and reviewing specifications, finding reliable sourcing partners and understanding… Read More
Open Silicon Delivers Silicon-Verified HBM2 IP-Subsystem on TSMC 16nm FF+
Open Silicon hosted a webinar today focusing on their High Bandwidth Memory (HBM) IP-subsystem product offering. Their IP-subsystem is based on the HBM2 standard and includes blocks for the memory controller, PHY and high-speed I/Os, all targeted to TSMC 16nm FF+ process. The IP-subsystem supports the full HBM2 standard with… Read More
Yield Analysis is a Critical Driver for Profitability
One of the most important aspects of any manufacturing effort is the yield of the process. Today, the investment in facilities, equipment and materials is so high that consistently high yields are vital to the profitability of the semiconductor manufacturer. Furthermore, the engineers must get to that consistent high yield … Read More
Improved Memory Design, Characterization and Verification
My IC design career started out with DRAM design, characterization and verification back in the 1970’s, so I vividly recall how much SPICE circuit simulation was involved, and how little automation we had back in the day, so we tended to cobble together our own scripts to help automate the process a bit. With each new process… Read More
Partitioning for Prototypes
I earlier wrote a piece to make you aware of a webinar to be hosted by Aldec on some of their capabilities for partitioning large designs for prototyping. That webinar has now been broadcast and I have provided a link to the recorded version at the end of this piece. The webinar gets into the details of how exactly you would use the software… Read More
What does the Lattice rejection mean for chip M&A?
Although the rejection of the Lattice deal was expected, it none the less has an impact on a number of dynamics in the chip industry and further M&A and consolidation. Freezing out China removes a “catalyst” in the market which help bid up values and add fear to both potential targets or those left out. Cross border… Read More
ATopTech is Back!
One of the biggest surprises at the TSMC OIP Forum last week was the reappearance of bankrupt EDA vendor ATopTech. I spoke with former ATopTech CEO and now Avatar IS President Jue-Hsien Chern at OIP. As a survivor of several EDA legal battles myself, I understand what ATopTech went through and I am thoroughly impressed that they had… Read More
Should the US Government Invest in Intel?