Hard IP for an embedded FPGA

As Moore’s Law enables increased integration, the diversity of functionality in SoC designs has grown. Design teams are seeking to utilize outside technical expertise in key functional areas, and to accelerate their productivity by re-using existing designs that others have developed. The Intellectual Property (IP) industry has emerged, where IP vendors offer design cores to SoC teams for integration. Specifically, “hard IP” refers to a core with a physical implementation, which has been optimized for performance, power, and area in a specific target process technology. Correspondingly, Moore’s Law also implies that the amount of programmable logic available in an embedded FPGA has expanded. It would make sense that SoC design teams leveraging the unique capabilities of an eFPGA would likewise be seeking to incorporate/re-use existing IP designs.

I’ve been having coffee periodically with the team at Flex Logix, to try to stay current on the rapidly expanding eFPGA industry segment. I asked Geoff Tate, CEO, and Cheng Wang, Senior VP Engineering, whether there is indeed a confluence of eFPGA customers and IP providers.

“Absolutely.”, Geoff replied. “Our customers are seeking the expertise of outside sources of IP, such as for functional accelerator cores.”(Refer to an earlier article on how eFPGA technology can provide a significant speedup on specific algorithms, compared to a software implementation on a microprocessor core – link.)

I asked Cheng,“How does the IP provider develop the implementation? What models are delivered to the end customer?” He replied, “The IP for an embedded FPGA is developed using the same model compilation flow as the customer, with only a single switch setting to differentiate the physical implementation.”

Figure 1. Illustration of the connectivity of a “hard IP” design in a customer eFPGA design.

“Like the customer design, the IP based on a set of eFPGA tiles.”, Cheng highlighted. “The physical distinction for the IP design is that the input and output pins of the IP are designed for internal connections, not to the top-level drivers/receivers.”

(For more on tile design, and the allocation of internal connections and receiver/driver circuits at the tile edge for primary inputs/outputs, here’s a link to an earlier article.)

“Other than the floorplan pin location assignment restriction, the compilation of the IP design is the same.”, Cheng said. “This is indeed a ‘hard IP’ approach. The end customer receives the eFPGA bitstream for the IP to merge with the personalization of their design. PPA optimizations for the IP have been completed by the IP provider, as reflected in the delivered personalization. Within the compilation environment, the customer has no visibility into the black box physical model.”

Figure 2. eFPGA compilation platform — the IP model is delivered as a physical black box, with no internal visibility.

“What IP models are delivered?”, I asked. “In addition to the final bitstream, the IP compilation flow automatically generates the physical abstract and the timing abstract for the customer. We collaborate with the IP provider on a power model.”, Cheng replied.

“Although we’ve discussed an IP vendor delivering models to an end customer, this same methodology certainly applies to any customer seeking the productivity benefits to re-using an existing optimized design block.”, Geoff added. “They would create an IP library for internal use in the same manner.”

The Flex Logix team refers to their hard IP flow as the design of an eFPGA “virtual array”. The figure below highlights a recent test chip of a 7×7 tile configuration incorporating a 4×4 IP virtual array.

Figure 3. Illustration of a 4×4 virtual array integrated into a 7×7 tile eFPGA design.

The IC industry has rapidly adopted the technical (and economic) model of hard IP integration and re-use, to augment the expertise of the design team and boost their productivity. Thus, it is a natural extension that this same model is also being adopted as part of the increasing capacities of embedded programmable logic.

For more information on the Flex Logix virtual array methodology for hard IP design, please follow this link.

-chipguy