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Network on Chip Brings Big Benefits to FPGAs

Network on Chip Brings Big Benefits to FPGAs
by Tom Simon on 12-19-2019 at 10:00 am

The conventional thinking about programmable solutions such as FPGAs is that you have to be willing to make a lot of trade-offs for their flexibility. This has certainly been the case in many instances. Even just getting data across the chip can eat up valuable routing resources and add a lot of overhead. These problems are exacerbated when wide or fast transfers are needed. In ASIC based SoCs it is easy to add IP for high speed interfaces. However, in FPGAs valuable logic units are often used to implement these same interfaces. It turns out that using one type of solution that is used in ASICs for connecting blocks is also a big win for FPGAs. We see Network on Chip (Noc) used a lot for ASICs, and now they have found a home in FPGA’s. The number of benefits they provide may surprise you.

Achronix has written an interesting white paper that covers eight benefits that come from the addition of a NoC in their Speedster7t FPGA. Their NoC is specialized to address the needs of an FPGA. It is arranged in vertical and horizontal channels that travel through the FPGA core. Each channel has two uni-directional high speed buses that operate at 512 Gbps. The FPGA also retains its traditional FPGA routing structure. NoC Access Points (NAP) located at the row and column intersections are used to make connections to the NoC. The NoC connects to all external interfaces for memory and networking.

NAPs provide connection to high speed NoC

I won’t go through each of the eight benefits here, but I want to discuss a few of them.

Two of the benefits have to do with the ability to connect to PCIe and 400G Ethernet. Making a PCIe interface work in an FPGA requires detailed work to understand placement and routing to manage delays and throughput. With a NoC, much of the work that previously required time and FPGA resources is handled automatically. Not only is design time saved, but also testing and debugging is reduced.

400G Ethernet also gets a boost from the NoC. Using their new Packet Mode, incoming packets are cascaded across four independent 256 bit buses in parallel, so that packets are efficiently conveyed. Packets are interleaved across these four buses so the FPGA can efficiently keep up with the incoming data stream.

One of the surprising benefits relates to how multiple teams can work more efficiently on FPGA projects that contain a NoC. Traditionally team design has been difficult to perform because of conflicts in accessing interconnect resources in the FPGA fabric. With the Achronix Speedster7t NoC any design block in the FPGA can access any other through the NAPs connected to the NoC. This suddenly removes any issues with placement or interconnect resources from the design design considerations.

The Achronix white paper has several other surprising benefits relating to how their NoC improves the design process. The NoC together with their high performing FPGA fabric is a winning combination. This is especially true for machine learning applications because of the specially architected Machine Learning Processors (MLP) found in the Speedster7t. I suggest reading the white paper, entitled “Eight Benefits of Using an FPGA with an On-chip High-Speed Network”. It is available for download on the Achronix website.


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