This blog is my second blog from this year’s Linley Fall Processor Conference. The first two blogs focused on edge inference solutions. Achronix’s discussion was much broader than just AI/ML; it was about where FPGA’s have been going and culminated with a product announcement preview. I’ll get to the announcement in a moment, but first, let’s review the growth in FPGA and the markets it serves based on what Manoj Roge, Achronix VP of Product Planning & Business Development presented at the conference.
FPGA 1.0 was the first broad adoption of FPGA technology. The largest usage of FPGA technology was initially in “glue logic,” which is logic used to integrated various components into a system, last-minute adjustments to systems, and programmable IOs. The usage of FPGA technology grew dramatically from the mid-1990s until around 2017. FPGA 2.0 supported more complex functions than FPGA 1.0. For example, in EDA, we saw the growing use of FPGAs in prototyping, verification, and emulation. From FPGA 1.0 to 2.0, TAM (Total Available Market) grew from about $1B to $5B. But now FPGA technology is exploding as the number of growth areas is picking up dramatically. In the past year we have seen FPGA technology projected as an important piece of solutions in several areas including, data centers, edge compute, 5G infrastructure, and automotive, especially ADAS. Manoj implied we could see up to a 6x growth in FPGA TAM between 2018 and 2024.
Achronix is has been furthering the growth in FPGA usage by making the technology available in multiple forms. Achronix has made its FPGA technology available in chip form (Speedster7t), as IP for use as embedded FPGA (called eFPGA) in its Speedcore and as chiplets with its Speedchip FPGA Chiplets. That is many ways to access some very high-performance FPGA technology. Achronix didn’t simply rely on PPA (performance, power, and area) benefits of 7nm FinFET technology, but took a clean slate approach and did a grounds-up design to address the bottlenecks of traditional FPGAs. With Speedster7t, Achronix has reinvented high-performance FPGAs with three key pillars of architecture optimizations – making the compute efficient for Machine Learning Inference, designing the right memory hierarchy, and bandwidth and by efficiently transferring data between compute and memory through true two-dimensional Network on Chip (NoC).
At the conference, Achronix also mentioned VectorPath. This information was a bit surprising since VectorPath was not yet formally announced, but the press release did pop on October 29, 2019. The VectorPath™ S7t-VG6 accelerator card was part of a joint project between Achronix and BittWare, a Molex company. The VectorPath accelerator card will deliver high-performance and high bandwidth at dizzying levels for an FPGA. Pricing was not mentioned, but availability is expected at the beginning of Q2 2020. Features include:
- 400GbE QSFP-DD and 200GbE QSFP56 interfaces
- Eight banks of GDDR6 memory delivering 4 Tbps aggregate bandwidth
- One bank of DDR4 running at 2666MHz with ECC
- PCIe compliance and certification
- 20 Tbps 2D NoC inside the Speedster7t FPGA
- 692K 6-input LUTs
- 40K Int8 MACs that deliver >80 TOPs
- OCuLink – 4-lane PCIe Gen 4 connector for connecting expansion cards
There are some interesting choices here. The high-speed interfaces are what data centers are looking for now as they moved forward with 400GbE deployments. Card features have been thought through well so that enterprise-class customers can deploy confidently and future proof their designs with lot of application flexibility. It has been designed for both evaluation and high-volume production applications with the ability to even get this pre-integrated into a Dell or HPE server platform, speeding time to market.
Both GDDR and DDR4 are included, though I think it is the availability of GDDR6 memory support that is critical for highest-speed applications. As you see above, there is even more, but I am sure you get the point that this is seriously fast.
The Speedster7t FPGA family features a 2D network-on-chip (NoC) with more than 20 Tbps bandwidth capacity to efficiently move the data within the FPGA fabric and between the highspeed IOs and the FPGA fabric. The NoC supports AXI channels, so you are still using an industry-standard interface.
To use an FPGA, you need design tools. All the Achronix products mentioned above can be programmed using the ACE design software, which is included with the purchase of a VectorPath card. ACE handles IP configuration, place & route, timing analysis, bitstream generation/download, and in-system debugging. The synthesis technology is Synplify-Pro from Synopsys though you get it through Achronix. The VectorPath product also comes with a comprehensive board management controller, OS support (Linux or Windows), API, drivers, application examples, and diagnostic self-test. The ability to use the same FPGA code (RTL) and tools across all these FPGA products is a nice feature to have. You could develop code on an accelerator card, reuse parts of it in chiplets, or elsewhere – truly reusable IP, and it is your IP.
I have one more blog coming from the Linley Fall Processor Conference for 2019. If you are into processors, you should consider going to the spring conference. I don’t think the details are announced yet, but you should be able to find them here once they are available. The leading edge is showing up at this event.