Webinar on Tools and Solutions for Analog IP Migration

The commonly advanced reason for IP reuse is lower cost and shorter development time. However, IP reuse presents its own challenges, especially for analog designs. In the case of digital designs, once a new standard cell library is available, it is usually not too hard to resynthesize RTL to create new working silicon. For analog designs there are many more steps and essentially the design will have to be reoptimized to meet its performance specifications before it can work. A lot of companies wade into the waters of analog porting only to realize too late that they are actually stuck in a muddy and complex process.

At that point a couple of well-known and perhaps over used platitudes are apropos – “There is no substitute for experience” and “Use the right tool for the job.” Fortunately for designers looking to smooth out the process of porting analog designs, MunEDA has tons of experience in this area and has a set of tools ideally suited to the task. Their upcoming Webinar titled EDA Tools and Solutions for Analog IP Migration, Optimization and Verification comprehensively covers the entire process and includes information about many of the particulars that can make or break the process. The webinar will be offered on March 26^th at 10AM Pacific Time. MunEDA Vice President of Products & Solutions Michael Pronath will be presenting. His deep understanding of the topic and lucid presentation style make the entire flow understandable.

There are three stages, as alluded to in the webinar title. The first is porting the schematic, which is done by the MunEDA Schematic porting Tool (SPT). As Michael will point out in the webinar, it makes the tricky parts flow smoothly and reduces manual effort in many places. It helps maps new cell names for each of the devices used in the design. Rules can be set for mapping pins and pin locations. New device parameters can be set using expressions. The webinar shows the user interface for these operations. MunEDA has learned through experience many of the subtle issues that arise and have added features to SPT that work through them automatically.

At this point the user has a topologically correct schematic, but one that will not function properly or meet its specs. The circuit now needs optimization and tuning. Michael will show how the MunEDA WiCkeD tool suite is used to size and tune the circuit. For instance, some of the device geometry characteristics that need adjustment are: W, L, fins, fingers, R, C, etc. Also, device threshold values can be set. The goal is to meet specs over all PVT corners with optimal yield, power, area and reliability. Michael will show the user interface and illustrate how to run their optimizer to arrive at design that meets specs and is optimized according to the design criteria. The process is iterative but is managed automatically. He will include several examples from their major customers that show the effectiveness of the flow especially when there are design tradeoffs to be made.

MunEDA has a suite of analog verification tools that are used in the final step – verification. Michael will start by doing a fast corner search to find the worst-case corners. He uses their Worst-Case Operation (WCO) tool for this. It can find the worst-case condition for every spec and structural constraint. He will show the tool and explain some details of its operation.

Michael then will cover Monte Carlo Analysis (MCA) and how their solution generates quantile plots that visualize the probability distributions. The UI also makes it easier to link to the actual simulation runs that the user might be interested in. Another useful set of information they can provide is parameter influence analysis. Parameter sensitivity information is useful for understanding design behavior.

Lastly the webinar will discuss high sigma analysis. MunEDA’s high sigma WCA uses powerful optimization that work across a wide range of sigma values to quickly find the worst-case point for the design.  Their solution scales to large designs through the use of advanced machine learning techniques.

It’s extremely rare to find a single source for a solution to such a complex problem. MunEDA has done an excellent job of integrating all the needed elements. The webinar covers each step and goes into the details about how and why. Be sure to check out the replay HERE.

Also Read:

56th DAC – In Depth Look at Analog IP Migration from MunEDA

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Schematic porting – the key to analog design reuse