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cliosoft 2021
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ClioSoft at GenApSys

ClioSoft at GenApSys
by Paul McLellan on 08-06-2013 at 12:51 pm

 ClioSoft at GenApSys

GenApSys is a biotech company developing proprietary DNA sequencing technology. As part of that they develop their own custom sequencing chips. These have an analog component and like many people they use the Cadence Virtuoso analog design environment for this.

I talked to Hamid Rategh who is GenApSys’s VP engineering. In previous companies over the last 6 years he has used ClioSoft for design data management and so with this long history it was natural that they would make that choice again at GenApSys. Not surprisingly they are very satisfied with how it works. Much of ClioSoft’s technology is tightly integrated into Virtuoso (and all the other popular layout environments if that is your thing) so that it is not necessary to spend a lot of time interfacing directly with ClioSoft explicitly. If you change a cell, it gets checked out. If you create a new version it is tracked automatically and so on.

 

 ClioSoft at GenApSys

In the old days (i think this means pre-GenApSys) there used to be some speed problems with the ClioSoft environment but that is no longer an issue. The tools is very easy to use and all the engineers are very happy with it.

Although GenApSys doesn’t do all their development at a single site, they do host all the data on a single server, so from ClioSoft’s point of view it is not a multi-site implementation. For larger companies, ClioSoft does support distribution, with a local server at each site and all of the sites kept synchronized as the design process unfurls.

ClioSoft is a small company and one of the advantages of a small company is great support. Hamid praised ClioSoft for theirs. In a tiny company, support comes directly from engineering. In a mid-sized company, support comes from application engineers. And in a large EDA company, support comes from a dedicated support organization. At each step in that ladder the support gets worse but it is more scalable. It is obvious that every engineer running into a minor issue with Design Compiler can’t call the appropriate engineer, even though he or she might provide the best response—nothing else would ever get developed.

One thing ClioSoft does that its competitors do not is to have linked workarea. This makes a big difference to the amount of disk space required. This is less of a problem than it was a disks have continued to get cheaper (even faster than Moore’s Law and due largely to completely different technology breakthroughs) although management overhead for backups etc is still an issue. And Moore’s Law is making data size explode.

So I asked Hamid to summarize their experience in a few bullets:

  • past experience was very good
  • great support
  • a tool that does exactly what is promised (DWISOTC, does what it says on the can)

Also Read

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Agilent ADS Users, Find Out About Design Data Management

The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows

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