Interview with Brien Anderson, CAD Engineer

I first met Brien Anderson on LinkedIn because we share common groups and interests, so I decided to interview him and discover how CAD tools enabled IC design at Synpatics, a company with capacitive sensing technology used in smart phones, tablets and touch screens.

Capacitive Sensing

Brien Anderson, CAD Engineer

Q&A
Q: How long were you at SYNA and what role did you play there?
A: I was there for 4 years, and worked as a senior CAD engineer.

Q: What types of IC designs did your group design or support?
A: We designed full custom touch SOC for use in laptops, tablets, and smart phones.

Q: What are the end markets for SYNA?
A: Synpatics has products for the consumer market.

Q: How many different chip designs did your group design or support?
A: We designed only touch-based products.

Q: What is the range of design complexity for these chips?
A: I’d say that the designs were medium complexity with big A and little D.

Q: What does your IC design flow look like?
A: Our team used a top down design flow with Cadence AMS Designer. Both language-based and transistor-level AMS design were used.

Q: For DRC and LVS, what tools did you use?
A: Mentor’s Calibre tool was used for DRC and LVS, then Cadence Assura RCX extraction for analog, and Synopsys StarRC extraction for digital.

Q: Which SPICE simulators were used in these AMS designs?
A: Our circuit designers used several Cadence simulators: Spectre, Spectre APS and UltraSim.

Q: What part does data management play in your IC design flow?
A: Data management is used in a complete front to back, top to bottom design flow. It includes marketing, specifications, requirements, firmware, ATPG, test, PCB, and all design data.
Same applies if the same sram is used in multiple chips and so on.

Q: Which data management tools did your group use?
A: We used Cliosoft tools called SOS, and VDD.

Cliosoft SOS data management used with Cadence Virtuoso

Cliosoft Visual Design Diff (VDD) tool

Q: How do Cliosoft tools help your projects?
A: Well, any workarea can be populated with any tag for sandboxing and every designer could re-create the full chip ams simulation result that another designer created. There were no simulaiton artifiacts, and no design data integrity issues.

Q: Where were your design teams located?
A: We have designer spread out between Santa Clara, Texas and New York, so keeping everyone updated on a project was important.

Q: What tools did you use before Cliosoft for data management?
A: We had used: svn, IC Manage (at National Semi, in a group acquired by Synaptics in 2009), and cvs.

Q: Why did you choose Cliosoft tools?
A: Several reasons for using Cliosoft: no special hardare was required, no new IT concepts to learn, and practically 24 by 7 support.

Q: If you could change anything with Cliosoft tools to improve productivity, what would it be and why?
A: I would request an enhancement to the IP database tracker to share IP such as microcontroller, flash, sram, and rom across a family of chips. Say for example that you have a particular release of an avr microcontroller that is used in four different chips. It would be nice to have a “where used” function that tracks exactly which version of which ip is used in which release of each chip.

Summary

Brien Anderson supported a CAD tool flow at Synaptics for AMS designs using a mixed-vendor EDA flow from Cadence, Mentor, Synopsys and Cliosoft. Synaptics is a leading developer of human interface solutions for mobile computing, communications, and entertainment devices, with revenues of $548.2 Million in fiscal 2012, ending June 30.

A Brief History of EDA

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