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Cliosoft NEW Logo 2020 copy
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Managing Differences with Schematic-based IC design

Managing Differences with Schematic-based IC design
by Daniel Payne on 07-02-2012 at 2:41 pm

At DAC in June I didn’t get a chance to visit ClioSoft for a product update so instead I read their white paper this week, “The Power of Visual Diff for Schematics & Layouts“. My background is transistor-level IC design so anything with schematics is familiar and interesting.

The Challenge
Hand-crafted chip designs provide the highest performance and give the designer greatest control over silicon IP area and specs, however when you are part of a team of designers there is a need to communicate with other team members on what has changed on your schematic since the last version.

Approaches for Text Diff
When I started doing DRAM circuit design in the 1970’s we used colored highlighters during the compare of schematics versus the netlist. Word processors like the Microsoft Office suite added text comparison features so that as you worked on a document a history of what just changed could be seen.

Unix users have the diff utility, even my MacBook Pro today has diff on it for the occasional times that I use the terminal and need to compare text files.

In EDA you can even use an LVS (Layout Versus Schematic) tool like Calibre to compare two versions of a schematic or layout netlist and get some idea of what has changed.

Approaches for Graphic Diff
With a schematic-based design you need a visual way to markup your schematics or IC layout to see what has changed since the last rev. You could try several approaches for tracking schematic or layout changes:

  • Netlist your schematics into EDIF or SPICE files
  • On IC Layout do an XOR of the GDS versions

The netlist approach works only on Text, so you cannot really see what changed which is more intuitive.

The XOR approach shows you visually what changed on the layout, but not the difference on a schematic level which is more intuitive to a circuit designer.

The Visual Design Diff Approach
ClioSoft has created a visual diff tool that works in a Cadence Virtuoso design flow to quickly highlight what has changed on your schematic since the last rev.

You just click a new menu choice in Virtuoso under Design Manager to see changes to:

  • Nets
  • Instances
  • Layers
  • Labels
  • Properties

This new class of EDA tool can be used by both the circuit designer or the layout designer in determining what has changed between versions of either a schematic or layout. This kind of automation will eliminate hours and even days worth of manual work compared to the old way of managing changes manually.

In June 2011 ClioSoft added support for hierarchy in the visual diff tool, so now you can traverse all the levels of hierarchy of your designs and see the differences.

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