Last month in DAC I could see some of the top innovations in the EDA world. EDA is a key enabler for advances in semiconductor designs. Among a number of innovations worth mentioning (about which I blogged just after DAC), the integration of Mentor’s Veloce with ANSYS’ PowerArtist for power analysis of live applications caught my attention. We already know about Veloce as a versatile tool for hardware emulation and PowerArtist as a versatile tool for power analysis of SoCs from RTL level. What makes the combination of two interesting is that the power consumption in a device during actual running of an application can be accurately measured and analyzed much faster. So I was more interested in learning about how exactly the interface between these tools work.
Before I go into the interface details, let me briefly mention about ANSYS PowerArtist functionality. PowerArtist provides power analysis of SoCs at RTL level in different measures such as average or time-based power. Also power-critical vector selection can be done. The PowerArtist uses RTL Power Model (RPM) for RTL-driven physical power integrity. The PowerArtist Calibrator and Estimator (PACE) technology ensures that early RTL power estimates track the final gate-level power numbers. The PowerArtist provides interactive debugging for power and employs various techniques for power reduction at clock, memory and logic level.
The activity data for computing power is typically acquired from simulation testbench and stored in files with standard formats such as SAIF (Switching Activity Interchange Format), VCD (Value Change Dump) and FSDB (Fast Signal Database). The PowerArtist reads the data from these files for power analysis. Clearly the file based interface provides post-simulation power analysis and brings its own overhead in making the analysis slow and error prone. Moreover, these formats lack either in terms of accuracy or capacity; SAIF does not include temporal information; VCD has temporal information but is inefficient because it is a textual format; FSDB is both temporal and binary but its generation slows down emulators and simulators.
To overcome these issues, ANSYSand Mentordeveloped an innovative approach where the activity data stream of an application running in Veloce emulator is directly captured by PowerArtist through an streaming interface. Due to elimination of file-based interface, both the emulator hardware and power analysis software tools run order of magnitude faster with the accuracy of actual consumed power. A key advantage of this approach is that it enables early RTL power visibility and budgeting for live applications which is not possible with traditional file-based approach.
PAVES (PowerArtist Vector Streaming) is a new innovative RTL power socket that can connect with emulators and simulators enabling streaming activity transfer. The PAVES socket interface with Veloce emulator’s DRW (Dynamic Read Waveform API) has been demonstrated working well in 52[SUP]nd[/SUP] DAC. This enables early gate-level power verification for live applications and therefore decisions for power budgeting of derivative designs. Since PAVES can process activity in parallel with the application running in Veloce, the power analysis can be much faster and accurate.
This approach of power analysis and budgeting for live applications has been tested by early access partners and customers. The runtime performance improvement with this new approach compared to the file-based approach can be up to 4.25x among the designs shown in the table above. This performance improvement is without any compromise on RTL-to-gate power accuracy.
With PAVES PowerArtist can read switching data directly from any supported emulator running a live application and provide visibility into RTL power as well as perform gate-level power verification without any overhead of file-based transfer. This is another feather added into the growing importance of emulation-based verification of SoCs.
Pawan Kumar Fangaria
Founder & President at www.fangarias.com