Verifying PCIe 5.0 with PLDA, Avery and Aldec

Mike Gianfagna, a fellow SemiWiki blogger and a one-time colleague at Atrenta shared a useful piece of marketing advice. If your company is not the biggest fish in the pond and you want to appear more significant, team up with other companies to put on an event, say a webinar. Pick your partners so that you can jointly offer a larger, more rounded view of a current topic than any one of you would be able to provide on your own. Which will automatically draw more registration and views. A pretty powerful idea that small companies should exploit more often. Aldec, PLDA and Avery did just that, in a joint webinar on verifying PCIe 5.0. There’s power in numbers.

PLDA

PLDA is a European-based company with offices in Silicon Valley. They specialize in high-speed interconnect IP: PCIe, CCIX, CXL and GenZ primarily, designed for implementation in FPGA or ASIC applications. They’re cagey about customers, as small companies usually are. They have presence in Europe and the US, now also in Asia. And they recently announced a design win on 5nm. PLDA supplied the PCIe 5.0 core used at the heart of this webinar/demo.

Avery

I knew of Avery many years ago, founded by Chilai Huang, previously of Gateway Design (the people who started Verilog) and Cadence. Chilai started Avery after he left Cadence, with a focus as I remember on symbolic simulation. This is still offered I believe in SimXACT, with an emphasis on X-verification. More interesting though in this context, they offer quite a broad range of VIP and they claim they are leaders in NVMe and CCIX/CXL, all of which I believe are founded on PCIe. So Avery provided the PCIe 5.0 VIP for this webinar/demo.

Aldec

I’ve written before on Aldec. They are a venerable EDA company, founded in 1984 and based in Henderson, Nevada. Again, they’re not especially open about customers, but I believe they are quite heavily used in FPGA design, especially in mil-aero applications (they have a big focus on DO-254 compliance and requirements tracking). I have no doubt that some of those designs transition to ASIC so they cover both implementation options. They have a full-range solution for FPGA design, simulation, emulation and prototyping. They also offer their own development and prototyping boards, based on Xilinx Zynq devices. Aldec provided their Riviera-PRO simulation platform for this webinar/demo.

The Demo

The demo itself is pretty technical. All about how they build the DUT and testbench. And how they encapsulate the PCIe IP with a pipe box to feed in transactions. With the Avery bus functional model as a front-end to this process, generating transactions to feed that pipe box. While Riviera-PRO simulates the whole thing and monitors transactions, checks and the like. All far above my technical paygrade I’m afraid. You should watch the webinar to get the real meat.

Which brings me back to my original point. These three companies together were able to deliver a complete story. One that none of them could have delivered on their own. Worth remembering. You can register to watch the webinar HERE.

About Aldec
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com