PCI Express 6.0 Design Considerations and IP Implementation

PCI Express 6.0 Design Considerations and IP Implementation
by Daniel Nenni on 06-15-2021 at 3:41 pm

SoC designers, looking to get a jump start on their PCI Express (PCIe) 6.0 designs must be aware of several new considerations in addition to doubling of the data rate to 64 GT/s. Accessing a complete IP solution that offers optimized performance and seamless interoperability between the controller and PHY, achieving timing closure
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Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud

Using IP Interfaces to Reduce HPC Latency and Accelerate the Cloud
by Scott Durrant Gary Ruggles on 03-11-2021 at 6:00 am

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IDC has forecasted that over the next five years, the Global Datasphere — the amount of data that’s created, transferred over the network and stored each year — will increase by over 3X to 175 zettabytes (Figure 1). Much of this is driven by the Internet of Things (IoT), video applications (including video streaming,… Read More


Verifying PCIe 5.0 with PLDA, Avery and Aldec

Verifying PCIe 5.0 with PLDA, Avery and Aldec
by Bernard Murphy on 11-03-2020 at 6:00 am

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Mike Gianfagna, a fellow SemiWiki blogger and a one-time colleague at Atrenta shared a useful piece of marketing advice. If your company is not the biggest fish in the pond and you want to appear more significant, team up with other companies to put on an event, say a webinar. Pick your partners so that you can jointly offer a larger,… Read More


Machine Learning Drives Transformation of Semiconductor Design

Machine Learning Drives Transformation of Semiconductor Design
by Tom Simon on 05-14-2018 at 12:00 pm

Machine learning is transforming how information processing works and what it can accomplish. The push to design hardware and networks to support machine learning applications is affecting every aspect of the semiconductor industry. In a video recently published by Synopsys, Navraj Nandra, Sr. Director of Marketing, takes… Read More


CCIX Protocol Push PCI Express 4.0 up to 25G

CCIX Protocol Push PCI Express 4.0 up to 25G
by Eric Esteve on 06-08-2017 at 12:00 pm

The CCIX consortium has developed the Cache Coherent Interconnect for Accelerators (X) protocol. The goal is to support cache coherency, allowing faster and more efficient sharing of memory between processors and accelerators, while utilizing PCIe 4.0 as transport layer. With Ethernet, PCI Express is certainly the most popular… Read More