Ohad Agami is the co-founder and CEO of Hiveware, a semiconductor verification company he started in Tel Aviv in 2023 with CTO Yaniv Pascal. He has a systems-focused engineering background with deep experience in semiconductor architectures and complex verification flows, built at the AI chip company Hailo and earlier in Israel’s Unit 81, and he brings a rigorous, algorithmic approach to problems EDA has long treated as unavoidable. Under his leadership Hiveware has raised $24M and built a team of roughly 30 engineers around one mission: attacking the simulation runtime that gates modern chip verification.
Tell us about your company?
Hiveware was founded in 2023 in Tel Aviv. My co-founder Yaniv Pascal, our CTO, and I started the company on one stubborn observation: digital simulation performance has been essentially flat for three decades while SoC complexity grew from millions of gates to hundreds of billions. The tools largely did not change; the chips did. We raised a $24M and built a team of roughly 30 engineers focused on a single problem, simulation acceleration. Our product, HiveSim, is a next-generation SystemVerilog simulator built from a blank page for modern multicore compute and cloud scale, rather than patched on top of a 30-year-old architecture. It is pure software, with no GPUs, emulation, or specialized hardware required to deliver large gains.
What problems are you solving?
Verification sits on the critical path to tape-out, and it is the part of the schedule that quietly holds everything else back. Full-chip and cluster-level regressions stretch from overnight into days and weeks, debug spills out of working hours as engineers wait on slow re-runs, and even well-run teams run their compute fleets at under 40% utilization. The industry’s workaround has been to push workloads onto emulation, trading millions of dollars and limited capacity for speed while giving up observability and debug depth. We attack runtime directly. HiveSim delivers roughly 5-10x on a single core and aims to more than 100x with multicore, design dependent, on the CPU infrastructure teams already own. That pulls long simulations back into the working day and off the critical path.
What application areas are your strongest?
Anywhere simulation time is a genuine bottleneck, which today means long-running full-chip and cluster-level verification. Think large AI accelerators, big CPU and GPU SoCs, Mobile, Automotive and any other large design, the cases where the design plus the testbench no longer fits in the overnight window. These are the tests that take hours, days, or weeks and sit directly on the path to tape-out. Because HiveSim is software simulation, teams keep full signal visibility and flexible debug, exactly what they lose when they are forced onto emulation. We integrate into existing SystemVerilog and UVM flows rather than asking teams to rewrite anything.
What keeps your customers up at night?
Schedule risk driven by verification runtime and debug time. Every day verification slips is a day added to tape-out and another window for a bug to escape to silicon. Verification leads worry about whether they can run enough cycles before the deadline, and about the cost and queue time of the emulators they lean on to compensate. There is also the quieter frustration of paying for large compute fleets that sit idle because legacy simulators cannot scale across them. The fear underneath all of it is the same one: that the limiting factor on the whole program is not the design team’s creativity but the speed of the tools verifying their work and the number of debug cycles that can be done a day.
What does the competitive landscape look like and how do you differentiate?
The simulation incumbents are Synopsys VCS, Cadence Xcelium, and Siemens Questa, with emulation and prototyping platforms such as Palladium, ZeBu, and Veloce on the acceleration side. Those simulators are mature and capable, but they carry decades of architectural baggage and were never designed for today’s core counts. We took the opposite path and rebuilt the engine from first principles to be parallel-native. Our differentiation is threefold. First, performance on standard CPUs, with no special hardware to buy or schedule. Second, we do not try to replace emulation hardware; we reclaim workloads that were pushed onto emulation because simulation got too slow, and we hand back full debug visibility in the process. Third, we drop into existing flows. The result is more verification cycles per dollar on machines our customers already own.
What new features/technology are you working on?
The biggest lever in simulation is not raw horsepower, it is wasted work. At any given moment, most of a large design is sitting idle. HiveSim is built around a different instinct: put compute where the design is actually doing something, and stop paying for the parts that are quiet. That is the foundation. Multicore scaling then sits on top of it, spreading the work that genuinely matters across as many cores as a customer wants to bring. Everything on our roadmap pushes the same idea further, deeper scaling, broader SystemVerilog and UVM coverage, and that same instinct applied to more of the verification flow. The ceiling here is high, and most of the climb is still in front of us.
How do customers normally engage with your company?
It is a hands-on, proof-driven process, not a slideware sale. An engagement begins with secure remote access and IT enablement, after which we take a real cluster-level or full-chip use case and validate measurable performance gains on the customer’s production-grade verification workloads. We believe the only number that matters is the one measured on the customer’s own design and testbench, so that is where we start. Teams that want to begin can reach us through hiveware.io.
CONTACT HIVEWARE
info@hiveware.io
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