Mohit Gupta founded TYLsemi to build chiplet-based intelligent power and connectivity solutions for AI infrastructure—an area where custom silicon has long been underserved. TYLsemi exists to provide the foundational chiplet platform that enables tailored custom silicon solutions for the evolving needs of AI infrastructure.
Most recently, Mohit served as Executive Vice President and General Manager at Alphawave Semi, where he was part of the executive leadership team that grew the company into a global provider of high-performance connectivity IP and custom silicon for AI and HPC applications. Alphawave Semi was acquired by Qualcomm in 2025.
Prior to Alphawave, Mohit was Senior Vice President and General Manager of the OpenFive business unit at SiFive— a custom ASIC and connectivity IP business that was acquired by Alphawave Semi in 2022. Earlier in his career, he held engineering and management roles at Rambus, Open-Silicon, Infineon Technologies, and STMicroelectronics.
Tell us about your company.
We founded TYLsemi to redefine how chiplet-enabled custom silicon is built by providing AI infrastructure customers with a faster, lower-risk path from architecture to deployment. We are delivering a full portfolio of chiplets across IO, power delivery and memory to enable customers to integrate proven silicon building blocks instead of designing critical components from scratch. This will accelerate development and reduce time-to-market, driving down development time and cost for AI infrastructure silicon by nearly 50%.
Our founders have shipped more than 30 million chips, closed over $1B in orders, and completed more than 75 high-volume designs with first-pass success. We have a 15+ year relationship with TSMC and close alignment across OSATs and IP partners. That track record shapes how we build products and support customers.
We officially came out of stealth mode in July 2026, at which time we also announced an oversubscribed seed round with total funding of $43 million.
What problems are you solving?
The AI accelerator market is on track to reach $604 billion by 2033 and custom silicon XPUs built for specific hyperscaler workloads is the fastest-growing segment. At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon.
Chiplets are the new form factor of physical IP for developing custom silicon.
What are the barriers to designing custom AI silicon, and how are you overcoming them?
AI systems are shifting from monolithic chips to distributed, multi-die architectures as chip size approaches physical limits and connectivity and power become bottlenecks. At the same time, advances in packaging technologies are making it possible to integrate multiple dies into a single system. With the emergence of standardized interconnects such as UCIe, chiplet-based design is now practical and scalable.
By replacing fragmented IP, design, and manufacturing workflows, TYLsemi reduces integration risk and complexity and provides a predictable path from architecture to deployment. For customers who need a complete solution, TYLsemi can extend chiplets into full custom silicon, delivering complete, production-ready systems.
What application areas are your strongest?
Our core focus is AI infrastructure: the XPUs, scale-up networks, and high-density compute systems driving the most demanding multi-die design challenges today. Below are the first chiplets we plan to bring to market:
- IO™: Versatile connectivity chiplet product family for AI systems
Comprehensive family of IO chiplets designed to enable high-bandwidth, standards-based connectivity across high-performance systems supporting PCIe, ESUN, and UALink connectivity today, with a co-packaged optics (CPO) roadmap for next-generation rack-scale fabrics. - Power™: Intelligent in-package power delivery solution for XPUs
An integrated voltage regulator (IVR) chiplet that provides efficient and intelligent control and optimized system-level power efficiency. - Mem™: Versatile memory connectivity product family for AI systems
A planned product family focused on memory connectivity for advanced AI systems, with additional details to be announced as the roadmap progresses. - Forge™: End-to-end chiplet-enabled custom silicon platform
A full-stack platform for customer-defined XPU, compute, and fabric designs, which TYLsemi implements using its connectivity and power delivery portfolio, plus IP, foundry, packaging, and production readiness.
What keeps your customers up at night?
Three things come up consistently.
- Time to silicon. AI infrastructure moves fast, and a program that slips six months does not just miss a schedule; it misses a market window. Customers need to compress design cycles without compounding risk.
- Integration complexity. Moving from a monolithic SoC to a multi-die architecture means managing chiplet interfaces, packaging constraints, die-to-die interconnect, and power delivery simultaneously, often with teams doing it for the first time.
- Supply chain confidence. Knowing a chiplet will be available at volume, at cost, with predictable yield requires a qualified, ongoing supplier relationship. That is why we secured a foundry partnership with TSMC, which recognizes a clear need in the market for our chiplet portfolio.
TYL.Forge was built around these pain points above, bringing foundry, OSAT, chiplets, and IP under one coordinated program.
What does the competitive landscape look like and how do you differentiate?
Hyperscaler-captive chiplets are unavailable to the broader market and large merchant vendors have roadmaps built for their own product lines. EDA companies provide tools. IP companies provide blocks. Design-services firms build custom chips one at a time, with the customer absorbing integration risk. Power delivery is also a growing gap in the market — AI workloads are driving energy demands that expose the limits of conventional in-package power architectures, and no existing vendor has a purpose-built chiplet solution for it.
TYLsemi occupies a different position: a pure-play chiplet product company offering pre-validated, production-ready chiplets as reusable silicon building blocks, available to any team building advanced custom silicon.
Three things set us apart. We deliver real silicon: KGD-screened chiplets customers can integrate today, not design files requiring further qualification. We are built on open standards — UCIe, PCIe, and Ethernet — giving customers interoperability without lock-in. And our model is product-led: the same chiplets customers integrate directly also form the foundation of our TYL.Forge custom silicon, so IP, qualification, and execution are reused across programs.
What new features/technology are you working on?
We are extending the TYL product family to cover more critical SoC functions, including memory expansion and scalable connectivity. We are advancing the TYL.IO family toward scale-up versions and second-generation 448G speeds, while expanding TYL.Forge for customers that need a complete path from architecture to high-volume production backed by a resilient supply chain.
We are also deepening ecosystem integration to bring closer alignment with packaging and OSAT partners, tighter coordination through our TSMC relationship, and qualification work that shortens the path from chiplet selection to deployed silicon.
How do customers normally engage with your company?
Customers can use these chiplets as standalone components or as the foundation for enabling full custom silicon solutions based on leading industry foundry and packaging technologies. Engagements typically begin with an architecture conversation. Customers bring a system challenge — an AI accelerator, a next-generation SoC, a supply chain concern — and we work through it together, scoping needs such as connectivity, power-delivery constraints, and whether chiplet integration or a full custom silicon program is the right path.
TSMC CoWoS versus Intel EMIB Semiconductor Packaging