WP_Term Object
    [term_id] => 76
    [name] => Tanner EDA
    [slug] => tanner-eda
    [term_group] => 0
    [term_taxonomy_id] => 76
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 60
    [filter] => raw
    [cat_ID] => 76
    [category_count] => 60
    [category_description] => 
    [cat_name] => Tanner EDA
    [category_nicename] => tanner-eda
    [category_parent] => 14433

High resolution Analog CMOS IC Design

High resolution Analog CMOS IC Design
by Daniel Payne on 10-04-2013 at 5:02 pm

My background includes transistor-level IC design, so I take delight in talking with engineers like Dr. Lanny Lewyn that are still practicing the art and science of analog IC design. Dr. Lewynis a Life Senior Member of the IEEE and has a consulting business. If you live in Santa Clara, then consider attending a live seminar on October 24th at Techmart, it’s sponsored by Tanner EDA and SemiWiki founder Daniel Nenni will also be present along with Eric Kurth, Design Manager at FLIR Systems.

Dr. Lanny Lewyn


Q: What kind of projects do you work on?

My projects focus on high speed, high resolution analog CMOS IC design. The circuits have ranged from single circuits, like high speed, high resolution comparators and physical-layer interfaces including low power 6GBS SERDES, to more complex circuits such as ADCs and DACs. I also like to use TCAD tools (Silvaco ATLAS) for modeling and design of minimum-area substrate decoupling isolation patterns and very-low-capacitance ESD structures for analog I/O.

Q: Where are your products used in the industry?

For the past 10 years it has been high resolution imaging and telecom. The imaging application was for space telescope applications (Hubble and the next-generation space telescope – the James Webb Space Telescope = JWST). The telecom applications have ranged from the first HDSL front-end qualified in the US and Europe to ADSL and then to 10GBS fiber modems. While the Hubble and JWST ADCs were 16b designs at very low power (1.5mW) and low speed, the present telecom ADCs are up to 14b and can run from 1GSPS in 28nm to up to 4 or 8 GSPS in a 4 or 8-lane configuration.

 ADC Layout presented at CMOSET 2013

Q: What are the biggest challenges to complete your projects?

In the early days it was the circuit design and achieving precision in the weighting networks (capacitor or resistor arrays) used in the DACs that were part of the ADCs. In deep-nanoscale the design challenge is definitely the physical design. In fact, I believe the challenges involved in deep-nanoscale physical design are the far more difficult than the circuit design. And that even includes the challenges of operating at low voltages and dealing with the analog variations in very-small-area devices. I reported on those challenges in “Analog Circuit Design in Nanoscale CMOS” in the Proceedings of the IEEE, October 2009.

In the sub-28nm technology nodes, it is now well known that single-exposure DUV lithography fails. The layout features then have to be decomposed into 2 or 3 separate patterns. In order to avoid unbelievably high computational lithography costs and schedule delays when the physical designs cannot be decomposed, we have to learn how to do physical designs that are, or can be easily decomposed.

There has been reported several instances of very low yields at 28nm as a result of systematic errors in physical design. This issue is particularly relevant to analog CMOS design where precision circuits are subject to variation from lithographic and stress effects. To make matters worse, these effects are not currently modeled in tools that are commonly used by the circuit designer. The use of regular design fabrics which incorporate pitch regularity and area uniformity are key elements in overcoming the effects of systematic errors. However the creation of these regular patterns requires the circuit designer to dimension the devices in such a way that pattern regularity can be achieved.

The bottom line here is that the circuit designer has to be involved in, or be doing the physical design at the beginning of the design cycle. When I lecture on deep nanoscale physical design for the Mead Education Group in Lausanne, I lightly mention that someone who wants to be a member of an Olympic track team does not start training a half-year before an event. Analog CMOS circuit design engineers cannot wait to learn and become heavily involved in the physical design only when they are given a PDK to do their next circuit in deep-nanoscale.

Q: What is your general IC design process?

I use dimensionless design for both schematics and layout. I reported on that in some detail in SMACD 2006 (symbolic methods for analog design). The advantage previously used to be to be able to design one or two technology nodes ahead. Now, with the high cost of test chips in the deep-nanoscale nodes being so high, it is an advantage to be able to port backwards to earlier technology nodes such as 90 or 180nm. My most recent ADC is presently being considered for an earlier-technology imaging application. Since Tanner L-Edit was originally designed to have dimensionless layout capability, its use is very natural for my approach.

My physical design is done in portable layout rules, which I call GAMMA rules. I reported on this methodology at SMACD 20106. Rather than use the granularity of ½ gate length (LAMBDA rules) introduced by old EE Prof. Carver Mead at CIT, I have found that using ¼ gate length gives me a more efficient use of area. The granularity of ¼ gate length also gives me the ability to use one physical design data base that fits the pitch constraints of 90/65/45/28 rules. The schematic capture is done in ‘F UNITS’ where F is one unit feature size, or gate length. Both schematic and layout dimensions can be adjusted in the final porting to a particular process. But once the adjustment parameters are set up, I can easily switch between simulations in any of the targeted processes.

Q: How do Tanner EDA tools fit into this IC design process?

I do all my layout in dimensionless physical design using L-Edit.I started using L-Edit many years ago to do just small cells that would help guide the layout process in areas where the physical design needed to be optimum. When the customer for the Hubble ADC couldn’t find an analog layout designer to do the job, I volunteered to give it a try. It really wasn’t that difficult using L-Edit. It is very user-friendly and has a user interface that makes editing a very easy and natural process. I wish my schematic editing tools had many of the features of my layout editor.

When I was finishing up the layout job for the space telescope ADC in 2002, I had previously promised 2 of my kids a week each in Paris. Being able to load my L-Edit into my 13” Toshiba Laptop provided the key to my keeping to the layout schedule (by working from 6am to 2pm) in Paris. It for sure would have been impossible to do that by lugging around a UNIX-based PC tower in my briefcase.

Q: How long have you been using Tanner EDA tools?

Over 20 years.

Q: Why did you choose Tanner EDA tools?

a. Ease of use (L-Edit). The graphics user interface is very natural –
b. Being able to use it on my lightweight portable PCs –
c. And cost.

Q: How is support from Tanner EDA?

It is excellent. I used several tools for IC design from other vendors, and the support I get from Tanner is right up there with the best of the best. When I have asked for some special code to be built to solve a unique problem, the folks at Tanner have jumped right on the job. And that is a unique experience for me.

Q: What will success look like for you 12 months from now?

I have transitioned my business model form doing consulting at an hourly rate, to developing my own IP. Using the dimensionless layout and circuit design capability of my present ADC IP, I expect that success will be seeing the same circuit and layout patterns used in two very different kinds of applications. It will be first used in a very high-resolution, low-power imaging application ported to an older technology. And the other application is projected to be a lower-resolution very high speed (4-8 GSPS) telecom application in a highly-scaled technology node such as 28nm.

High resolution analog CMOS IC design can be implemented using Tanner EDA tools across a wide range of process nodes, and Dr. Lewyn has been creating many designs with a dimensionless methodology. You’re invited to a live seminar at Techmart in Santa Clara on Thursday, October 24th to hear from two analog designers about their best practices.

lang: en_US

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.