Chips Are Going 3D, DRC Needs to Go 3D Too

The last paradigm shift in DRC was around 0.35um when designs got too large to handle as flat data, and hierarchical approaches were required. Back then the design rules themselves were not that complex, the explosion of data volume came from the complexity of the design itself. But each process node added more design rules intricacies and many new types of rules that needed to be checked.

Until recently, design rule complexity has been increasing around 20% per node (plus the designs continue to get bigger, of course). Now, advanced technology node complexity has exploded either due to FinFETs (for SoCs) or 3D NAND flash and much deeper trenches for DRAM (for memories). The world has gone 3-dimensional, and it’s getting very difficult to use inherently 2D checking methodologies to find 3D design problems. Often a single 3D “problem”, when abstracted to 2D DRC syntax, can drive thousands of individual design rules and entire chapters in a design manual. Since design rules have to account for small but inevitable variations in the manufacturing process, the development of these rules needs to understand the complex relationship of structure to process and design in 3D. For example, it is extremely difficult by examining the mask designs to verify that the fin height of the FinFET produced by those masks is within tolerance…or that this fin height variation won’t cause gate shorts to nearby devices. In effect, there has to be a very indirect and inefficient model of the manufacturing process hidden away in the rules and the DRC algorithms.

Coventor has a product, SEMulator3D that is inherently three dimensional. SEMulator3D is a virtual fabrication platform that many foundries and memory companies use to speed advanced semiconductor processes to market. Relying exclusively on test wafer manufacturing is too expensive and too slow for the continued fast pace and competition for advanced semiconductor products. When SEMulator3D is used for process development it reads in layout and a description of the process recipe and produces a full predictive model of what is going to end up on the wafer. The underlying technology uses voxels (the volume equivalent of a pixel). This is just the foundation required to make a much more direct, accurate and efficient interrogation of the 3D structures on the chip.

Virtual fabrication can be used to augment the conventional DRC approach, which is well suited for some things, with a 3D approach that creates an accurate and predictive view of what those masks create on the wafer. New capabilities in SEMulator3D allow three dimensional rules to be applied to virtually fabricated models. For example, technology developers can build up a complete 3D FinFET based on the masks and then measure critical aspects such as the fin height, spacer thickness and gate isolation much more directly.

Coventor has been actively developing the SEMulator3D technology to apply these 3D design rules to advanced technologies and product designs. It has just been granted a patent in this area and is now expanding its relationship with customers and partners to advance this 3D checking technology to augment the current DRC programs. Of course, it will take time for this 3D checking technology to mature and be ready for production-level sign-off. However, it is already showing great promise. This promises to be the next paradigm shift in DRC technology and should considerably improve the creation and application of design rules in advanced 3D technologies.