SEMICON West – EUV Readiness Update

At the imec technology forum held at SEMICON West, Martin Van Den Brink, President and CTO of ASML presented on the latest developments on EUV. I also had an opportunity to sit down with Mike Lercel, ASML Director of Strategic Marketing for an interview.

ASML acquired Cymer to tie together the development teams and accelerate increases in EUV source power. Since the acquisition EUV source power has come up by 10x and six weeks before the show ASML showed 250-watts at the San Diego factory. 250-watt capability will ship out to customers later this year. For several years achieving 250-watts has been the single biggest EUV roadblock and ASML has now met this goal. Figure 1. presents the EUV throughput trend over time.

Figure 1. EUV throughput trend.

EUV with >100 wafers per hour (wph) is now shipping and the specification for the NXE3400B is 125 wph at 20mJ/cm2. ASML is on track to meet the 125 wph specification and they think they can go above 125 wph next year. For the first time, ASML is meeting all the specifications for EUV!

Another key EUV issue is line edge roughness (LER). 125 wph at 20mJ/cm[SUP]2[/SUP] is only useful if it comes with acceptable LER. To-date much higher doses have been required to achieve acceptable LER. At the imec technology forum An Steegen presented a slide showing a 32nm pitch printed with ~21 mJ/cm[SUP]2[/SUP]. The LER as printed was >5nm but after smoothing techniques were applied 2.4nm was achieved, see figure 2. Smaller pitches and dense contacts were also achieved although the dose for those was >30mJ/cm2.

Figure 2. EUV LER before and after smoothing.

Multiple pellicles had been fabricated with zero printed defects, see figure 3. Pellicles transmit approximately 80% of the incident energy and ASML has tested the current pellicle up to 140 watts. With hydrogen cooling ASML believes the pellicle will support 250 watts.

Figure 3. Pellicle progress.

At SEMICON West last year, worldwide EUV systems had exposed 600 thousand wafers, this year over 1.2 million wafers have been exposed with good pattern fidelity.

EUV is expected to provide lower cost versus complex multi-pattering schemes, at 7nm reduced process complexity is expected to provide better yield, EUV shows lower process variation versus multi-patterning for 7nm and the reduction in extra multi-patterning related processing will result in shorter cycle time and enable faster time-to-market. Last year in an interview I did with Gary Patton, CTO of Global Foundries he told me they were using EUV for non-transistor levels during their 7nm development to speed up the development process.

ASML has introduced a new NXT2000 immersion system providing matched overlay with EUV for 7nm, 6nm and 5nm production. The NXT2000 matches immersion to EUV for multi-patterning with EUV cuts. ASML expects that when EUV starts shipping for production, immersions systems will continue to ship and the two will need to work in concert. The latest alignment and leveling sensors are functionally the same on the EUV and immersion systems.

ASML expects to ship 12 or 13 EUV systems this year and around 20 systems in 2018.

After many years of research and development EUV is now on the cusp of entering production. TSMC and Global Foundries are both introducing 7nm processes based on immersion lithography but they are also developing follow-on improved 7nm process to take advantage of EUV. Samsung has bene the most aggressive in EUV adoption and their initial 7nm process will be EUV based and is expected to enter risk production in 2018. I even heard a rumor at the show that Samsung was going to start using EUV on one DRAM Layer this year!