At the IEDM 2017, imec held an imec technology forum and presented several papers, I also had the opportunity to interview Anda Mocuta director of technology solutions and enablement. In this article I will summarize the keys points of what I learned about the future of logic. I will follow this up with a later article covering memory.… Read More
At the imec technology forum held at SEMICON West, Martin Van Den Brink, President and CTO of ASML presented on the latest developments on EUV. I also had an opportunity to sit down with Mike Lercel, ASML Director of Strategic Marketing for an interview.… Read More
At the ISS Conference in January, An Steegen EVP of Semiconductor Technology & Systems at imec gave a talk entitled “Patterning Options for Advanced Technology Nodes”. I was present for her talk and had the opportunity to have a follow up interview with An.… Read More
At the VLSI Technology Symposium, IMEC presented a paper entitled “Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Silicon Wafers”. I have wanted to blog about this paper since the symposium was held but also wanted to tie it in with an interview… Read More
On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). In part 1 of this blog I discussed the introduction and the first two presentations given by An Steegen and Mark Rodder. In this blog I will discuss the final two presentations. Part 1 can be accessed here.… Read More
On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). The ITF was held at the Belgium ambassador’s residence, a really beautiful setting for a meeting.
The ITF began with a brief welcome by the Belgium ambassador followed by a brief introduction to IMEC. IMEC is a research institute … Read More
Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.
First off Vassilios really… Read More
