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IEDM Blogs – Part 7 – IMEC Technology Forum – Part 2

IEDM Blogs – Part 7 – IMEC Technology Forum – Part 2
by Scotten Jones on 01-08-2016 at 7:00 am

On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). In part 1 of this blog I discussed the introduction and the first two presentations given by An Steegen and Mark Rodder. In this blog I will discuss the final two presentations. Part 1 can be accessed here.

Aaron Theon
Aaron is vice president of process technologies and director of logic devices at IMEC and his presentation was entitled “Nano-Electronics Scaling for the Next Decade & Beyond”.

The vacuum tube to the transistor took 40 years. The transistor to the IC took 10 years. IC growth has been exponential fueled by diverse applications and requirements. A datacenter processor is 100 to 500 watts, a mobile process is 100 milliwatts to 10 watts.

Logic costs are going up:

  • N28 to N20 – 28%
  • N20 to N14 – 7%
  • N14 to N10 – 24%
  • N10 to N7 – 28%

At N7 interconnect is 70% of the cost.

Heterogeneous systems, no one size fits all transistors, evolve options. Research needs to be aligned to Moore’s law cadence of ~2 years. 10nm ~ 2016, 7nm ~ 2018, 5nm ~2020, 3nm ~ 2022. Need to start the research process really early.

  • N+1 – extending silicon
  • N+2 – extending silicon
  • N+3 – extending silicon + beyond silicon + beyond CMOS
  • N+4 – extending silicon + beyond silicon + beyond CMOS
  • N+5 –beyond silicon + beyond CMOS

Extending silicon – doping, epi, parasitics dominate scaling. Improve Fin contact resistance. Evolve fins from taper fin to straight fin to narrower fin to nanowires.

You can make nanowires from a Fin. First you create a fin that is a super lattice of germanium and silicon and then create the nanowires inside the fin.

Beyond silicon – tunnel FETs, defect engineering for III/V on silicon, defect trapping using V groove, traps follow groove walls. III/V can heat silicon. Quantum devices are very sensitive to defects.

Beyond CMOS – wiring congestion is a problem. Putting transistors close together leads to more wire. Rent’s rule, wire constrained by device boundary.

Layout restrictions – N14 to N7 adding more layers to create connections. Routing resource congestion, create 28 transistors with just 5 gates for a spin wave circuit.

Move away from charge based computing to spin based computing.

45nm HKMG introduced – concept 1990, production 2007
22nm FinFET introduced – concept 1998, production 2011

It takes 10 to 15 years to develop game changing processes and get them to production.

To deliver system value over diverse requirements needs device specialization.

You need:

  • Innovative options
  • Patience – 10 to 15 years
  • There is no more low hanging fruit
  • Infrastructure for manufacturing
  • Work collectively and collaboration

Gosia Jurczak

Malgorzata Jurczak is the director of RRAM and DRAM MIMCAP porgrams at IMEC and her presentation was entitled “Beyond 50 Year Moore’s Law: Memory Technology as an Innovation Incubator”

50 years of space walking and Moore’s law.

  • 1972 1Kb DRAM and today 4Gb + 20nm half-pitch
  • 1971 256b EEPROM and today 128Gb + <20nm half-pitch, also stacking

Memory is the trend setter in silicon technology:

  • 2007 3D access transistor
  • 2010 Air gaps NAND
  • 2011 3D stacking and through silicon vias
  • 2013 3D NAND stacking
  • 2008 to 2012 VFET in DRAM but hasn’t worked well

New trends in memory:

  • NAND planar 16nm to 12nm
  • 3D NAND 32 layers now, 48 to 64 layers 2016-2018, 96 to 128 layers 2018 to 2020
  • 3D stacking after 2020
  • 768Gb in 2018, 1.5Tb in 2020, 3Tb in 2022
  • Looking at vertical channel materials for read performance

Storage class memory:

  • Needs better performance than NAND
  • Scalability
  • PCM or RRAM
  • Selector is also key
  • Path to 3D

Embedded memory issues:

  • Embedded flash (eFlash) doesn’t scale well due to high voltage block
  • HKMG hard to do with eFlash due to thermal issues
  • eFlash is 9, 10 or 12 added masks
  • Looking at BEOL memory where a memory cell is built between metal layers with 2 to 3 masks
  • Requires a selector that can integrate into BEOL and allows memory array over logic
  • RRAM such as OXRAM, CBRAM or VMCO (OXRAM family). PCM or STTRAM
  • IMEC has RRAM and STTRAM programs

Want lower programming energy, 2 or 3 volts versus 10 volts, even 1 volt. Faster memories decrease energy. They see STTRAM and RRAM replacing NOR over time.

Working memory on SOCs is going up. A lot of die area is SRAM and >50% of power is SRAM. Replace SRAM with eDRAM for lower area and power but as you scale down the cell you need more frequent refresh. Replace with STTRAM that is nonvolatile, but needs faster write time.

They want to scale down STTRAM program energy. STTRAM memory cells require ~30 layers and many of them are hard to etch.

At IEDM IMEC presented multiple papers addressing all of these areas.

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