Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.
First off Vassilios really stressed the challenge of designing for 5nm and the need for collaborations like this one between imec and Cadence. Timing optimization and routing are very challenging! The IMEC/Cadence collaboration combines detailed process knowledge with EDA.
The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers. The chips had a dummy metal 1 layer and via 1, metal 2 (M2), via 2 (V2) and metal 3 (M3) layers. The M2 and M3 layers were really the focus of the work and the metal pitch was scaled down from 32nm to 24nm.
Three different patterning approaches for M2 and M3 that were evaluated:
The EUV approach used single exposure EUV to form the metal lines. The hybrid approach used argon fluoride immersion (193i) with self-aligned quadruple pattering to form the metal line patterns and then a single EUV exposure to define the metal line cuts. The 193i SAQP approach used argon fluoride immersion (193i) with self-aligned quadruple pattering to form the metal line patterns and then three separate 193i cut masks (3 color cutting) to form the pattern. A litho-etch-litho-etch-litho-etch (LE3) approach was used to pattern V2.
All three approaches were found to be viable. The Hybrid and 193i approaches both use SAQP to define the metal lines and require more dummy lines than the single exposure EUV approach which should lead to better performance for the EUV single exposure. However, things like Line Edge Roughness (LER) might be worse for EUV and negate the advantage.
Simulations included fins underneath and the resulting interconnect layers meet the timing needs for 5nm. The metal and barrier layers used were not disclosed. EUV throughput was also not disclosed but Praveen did say that imec is upgrading to an 80 watt source.
The images above are from an article by Debra Volger of SEMI The Roadmap to 5nm: Convergence of Many Solutions Needed where she quotes An Steegen, SVP of Process Technology, at imec:
“Imec is enabling the roadmap to 5nm via a multitude of process features in close co-optimization with the design to drive down to the required power performance and cost trade-offs,” Steegen noted. “We are convinced that we have identified building blocks to enable the roadmap from 10 to beyond 5nm. But it’s not a one-solution thing – it’s many things that need to come together.”
Here are the quotes from the Cadence press release in case you are interested:
“Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”
By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “With imec technology and the Cadence Innovus Implementation System, we’ve created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs.”
0 Replies to “IMEC and Cadence Disclose 5nm Test Chip”
You must register or log in to view/post comments.