On Sunday evening December 6[SUP]th[/SUP] before IEDM, IMEC held the IMEC Technology Forum (ITF). The ITF was held at the Belgium ambassador’s residence, a really beautiful setting for a meeting.
The ITF began with a brief welcome by the Belgium ambassador followed by a brief introduction to IMEC. IMEC is a research institute located in Belgium. IMEC was formed in the 1983/84 time frame and has an annual budget of approximately 400 million euro. The introductions were followed by the formal presentations.
The technical program of the meeting was really good, unfortunately IMEC will not let me share the presentations but hopefully I can do a good job of summarizing what was presented.
An is the Vice President of Process Technology at IMEC.
IEMC presented 23 papers at IEDM this year and everything is connected. There is a need for more bandwidth at lower energy.
Three keys are:
1) Dimensional – 0.7x scaling per generation. Argon Fluoride immersion lithography (ArFi) can achieve a pitch of approximately 80nm forcing multi-pattering for the latest generation processes. EUV can print 40nm or even 30nm with a single exposure. The 7nm logic node (N7) will have a 30-40nm pitch. For the 5nm logic node (N5) a 24nm pitch will be required driving the need for 1D patterns and EUV for cut/block (multi-patterning).
2) Devices – Silicon FinFETs currently. Next is FinFETs with III/V channels and then vertically stacked horizontal nanowires.
3) System scaling – 3D stacking provides smaller size, less power and more bandwidth. Longer term move to optical interconnect.
IMEC provides infrastructure, people and partnerships. IMEC at a glance:
- 200mm CMOS pilot line
- 300mm CMOS pilot line
- Expanding the cleanroon by 4,000m[SUP]2[/SUP]
- Doing research on the 3nm logic generation (N3)
- ~2,300 staff, ~1,500 on the IMEC payroll and ~800 from partners
IMEC papers accepted at IEDM have been 18, 17, 17, 19, 16 and 23 for 2010, 20122, 2012, 2013, 2014 and 2015 respectively.
Mark Rodder from Samsung’s Advanced Logic labs went next and presented a whirlwind tour of challenges to continuing Moore’s law (he seriously challenged my ability to rapidly take notes with an incredible information dense presentation).
In 1983 we thought 500nm was the economical limit. In 1986 the half-micron apocalypse paper was published. In 1989 the author of the 1986 paper said scaling will continue. The concerns were similar to today’s challenges, but there are more challenges today, Moore’s law is exponential.
In a “standard” cell geometry contacted poly pitch (CPP) limits cell width, and back end of line (BEOL) pitch and routing limits the cell height. Cell height limits active space (effective channel width or effective channel width per fin). Cell area limits contact and via area and interconnect length.
CPP scaling through higher mobility materials – unstrained germanium mobility is similar to strained silicon. Strained germanium has better mobility than strained silicon. III/V materials are similar. III/V materials are more susceptible to surface roughness scattering than silicon, germanium is less susceptible. CCP scaling with III/V is less than ideal due to scattering issues. Germanium can increase leakage due to band to band tunneling (BTBT). New structures can reduce leakage but need to fit.
Parasitics can dominate performance – reduction of source/drain volume can increase contact resistance and the fundamental contact resistivity may be higher than expected. Further reductions in contact resistance may be limited but we aren’t at the fundamental limit yet.
BEOL parasitics are more critical – via and line resistance are grand challenges for upcoming nodes. At this point a graph was shown that illustrated that for various copper interconnect line lengths the resistance with scattering is >2x the resistance without scattering. BEOL congestion is also a problem for cell scaling with 1[SUP]st[/SUP] and 2[SUP]nd[/SUP] order rules limiting scaling. New cell designs are needed.
On die cache – additional cache memory is needed to address the gap between logic and memory performance. STTRAM can address the additional cache needs and is more compact than SRAM (1T – 1MTJ versus 6T). SSTRAM can be stacked in the BEOL versus front end of line (FEOL) SRAM. STTRAM is nonvolatile but the error rate needs to be addressed for fast on-die applications.
All of the above should get us to 2025, but remember all the past predictions about Moore’s law.
The net of this is:
- Simple pitch shrinks are becoming more challenging.
- Hetero-integration can be useful but requires the right materials and parasitic resistances.
- BEOL has fundamental limits that need a breakthrough.
- Extending Moore’s law for several more nodes may be difficult by any one of these technique – we may need breakthroughs for each new node.
- System performance can be boosted by Moore’s law or Moore than Moore such as 3D stacking, dense/non-volatile memory, new circuit designs.
- TFETs – a steep sub threshold slope is possible.
- 2D materials – low temperature BEOL, band engineering, TFET use, etc., but requires materials and interface development.
- Advanced interconnects such as optical.
- New switches such as spintronics.
- Dry brains (neuromorphic computing) or another efficient hardware implementation. Co-processors are much more efficient for certain tasks.
The market opportunity is huge, only 3 billion people are connected, there are 4 billion people still to connect. Opportunities in connected cars (we spend >1 hours per day in them), wearables (smart watches, fitness bands, activity tracker, etc.) and smart devices (home energy, home security, appliances, etc.)
One projection of IoT is for 20 billion connected devices by 2020.
“Challenges & solutions notwithstanding, there are many opportunities for value from the ever increasing number of connected devices and diverse application space – Whether by Moore’s Law, or by More than Moore”
In the next installment I will cover Aaron Thean and Malgorzata Jurczak’s presentations.Share this post via: