The EUV Divide and Intel Foundry Services

The EUV Divide

I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.

If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production on their previous node (n-1) and ramping down the node before that (n-2 node). They don’t typically keep older nodes in production, for example, last year 10nm was n, 14nm was n-1 and 22nm was n-2. Intel had some 32nm capacity in Fab 11X but that has now been converted to a packaging Fab. This contrasts with someone like TSMC that built their first 130nm – 300mm fab in 2001 and is still running it plus their 90nm, 65nm, 40nm and 28nm fabs as well.

By the end of 2022 Intel should be ramping up their 4nm node, then in 2023 their 3nm node, and in 2024 their 20A (2nm) and 18A (1.8nm) nodes should ramp up. All of those are EUV based nodes and it would seem reasonable that by the end of 2024 Intel would have little use for non-EUV based processes for microprocessor production since their 7nm/10nm non-EUV nodes would be n-4/n-5 depending on how you treat 10nm/7nm.

If I look at Intel’s current and planned Fab portfolio, there are EUV capable fabs and older fabs that are unlikely to ever be used for EUV, in fact EUV tools require an overhead crane and many of Intel’s older fabs would likely require significant structural modifications to accommodate this, plus Intel is building 9 EUV based production fabs.

The following is a site by site look at Intel’s fabs:

• New Mexico – Fab 11X phases 1 and 2 are Intel’s oldest production fabs and they are being converted to packaging Fabs. 11X-3D may continue to operate for 3D Xpoint. Intel recently discussed two more generations of 3D Xpoint and this is currently the only place to make it.
• Oregon – Fab D1X phases 1, 2 and 3 now lead all of intel’s EUV based development and early production. Fabs D1C/25 and D1D are older development/production fabs that are unlikely to be converted to EUV and are currently being used for non-EUV production.
• Arizona – Fabs 52 and 62 are EUV fabs under construction. Fab 42 is currently running non-EUV nodes but it was built as a EUV capable Fab and will likely be used for EUV someday. Fabs 12 and 32 are production fabs running non-EUV nodes and will likely never be converted to EUV.
• Ireland – Fab 34 is an EUV fab under construction with equipment currently being moved in, this will likely be Intel’s first 4nm EUV node production site. Fabs 24 phases 1 and 2 are non-EUV production sites and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
• Israel – Fab 38 is an EUV fab under construction and will be a 4nm EUV node production site. Fabs 28 phases 1 and 2 are non-EUV node production and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
• Ohio – Silicon Heartland EUV based fabs 1 and 2 are in the planning stage.
• Germany – Silicon Junction EUV based fabs 1 and 2 are in the planning stage.

In summary Intel is in various stages of running, building, or planning the following EUV based fabs, D1X phases 1, 2 and 3, Fabs 42, 52, and 62, Fab 34, Fab 38, Silicon heartland 1 and 2 and Silicon Junction 1 and 2. That is 3 development fabs/phases and 9 EUV based production fabs.

For non-EUV fabs still running, Intel has D1C/25, D1D, Fabs 12 and 32, Fab 24 phases 1 and 2, and Fab 28 phases 1 and 2. That is 8 non-EUV production Fabs. This really puts into perspective why Intel would want to get into the foundry business and support trailing edge processes. All these fabs can be used to produce any of Intel’s non EUV 10nm/7nm and larger processes plus likely with reasonable changes in equipment sets any of the processes they will be acquiring from the Tower acquisition.

Déjà vu all over again

Yogi Bera is famous for being humorously quotable and one of his famous quotes was “it is Déjà vu all over again”.

The last time Intel tried to get into the foundry business they failed to gain much traction. Foundry was still a second-class citizen at Intel, they didn’t have the design eco system and eventually exited the foundry business. One of the things that bothered me about Intel’s effort and in my opinion sent a message to foundry customers that foundry was second class was that Intel would develop a new process node, for example 32nm, they would introduce a high performance version for internal use and then a year later introduce the foundry (SOC) version.

Recently I saw an interview with Pat Gelsinger where he talked about 4nm being an internal process for Intel and then 3nm being the foundry version. 3nm is currently expected to come out approximately a year after 4nm. He then talked about 20A as an internal process and 18A as the foundry version. 18A is due to come out 6 to 9 months after 20A. I don’t think foundry customers will accept always being 6 to 12 months behind the leading edge and I think it sends the wrong message. He did say if a foundry customer really wanted to use 4nm they could, but he seemed to view 4nm and 20A as processes that should be tested internally before the next version is released more widely.

I do think Intel has an interesting opportunity. There is a shortage of foundry capacity at the trailing edge where Intel will likely be freeing up a lot of fab capacity and there is a shortage at the leading edge as well. In addition to that, there is a need for a second source at the leading edge. Samsung has a long history of over promising and under delivering on technology and yield. Companies like Qualcomm have repeatedly tried to work with Samsung, so they aren’t wholly dependent on TSMC and have been repeatedly forced back to TSMC. The latest example is the Qualcomm’s Snapdragon 8 gen 1 that is reported to have only 35% yield on Samsung’s 4nm node. If Intel can execute on their technology roadmap in a consistent basis with good yield, they can likely pick up a lot of second source and maybe even some primary source leading edge business particularly at Samsung’s expense. I could even see a company like Apple giving Intel some designs to strengthen their negotiating position with TSMC. I wouldn’t expect MediaTek, a Taiwan company located near TSMC, or AMD or NVDIA due to competitive concerns to work with Intel, but never say never.

EUV  shortage

As I mentioned at the outset it is a EUV supply and demand analysis I have been doing that triggered EUV gap ideas. As I outlined above Intel plans to build out and equip 9 EUV based Fabs. At the same time TSMC 5nm is widely believed to have ended 2021 at 120 thousand wafer per month capacity. TSMC has announced they expect to double the end of 2021 capacity on 5nm, by the end of 2024 and that is before the Arizona 5nm fab comes online. TSMC has talked about 3nm being an even bigger node than 5nm. TSMC has also started planning on a 4 phase 2nm fab with a second site in discussion. Samsung started using EUV for one layer on their 1z DRAM and then 5 layers on their 1a DRAM. Samsung is planning a new EUV based logic fab in Texas and is building out logic and DRAM capacity in Pyeongtaek. SK Hynix has started using EUV for DRAM, Micron has pulled in their DRAM EUV use from the delta to gamma generation and even Nanya is talking about using EUV for DRAM. This begs the question, will there be enough EUV tools available to support all these needs and my analysis is that there won’t.

In fact, I believe there will be demand for 20 more EUV tools than ASML can produce each of the next 3 years. To put that is perspective, ASML shipped 42 EUV systems in 2021 and is forecasting 55 system in 2022. Interestingly I saw a story today where Pat Gelsinger commented that he is personally talking to the CEO of ASML about system availability and admitted that EUV system availability will likely gate the ability to bring up all the new fabs.

I think another impact the EUV system shortage will drive is a different view of what layers to use EUV on. If a layer is currently done with multi-patterning more complex than double patterning EUV is generally cheaper. EUV also enables simpler design rules, more compact layouts, and potentially better performance. EUV will be even more important as the switch is made to horizontal nanosheets. I believe companies will be forced to prioritize EUV use to the layers where it has the most impact and continue to use multi-patterning for other layers.

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