Strong Overall Market Growth but a Slowdown Looms
After six years of single digit percentage growth in the overall semiconductor market, 2017 saw almost 22% growth and 2018 year-to-date is up roughly 17% (based on numbers published by the world semiconductor trade statistics). The big growth driver the last two years has been surging memory prices driven by high bit demand and tight supply. With additional memory capacity coming on-line, memory supply is expected to ease in 2019 removing the biggest driver of growth. Depending on whose forecast you believe the overall semiconductor market for 2019 may show single digit percentage growth or a single digit percentage decline.
Leading Edge Logic Down to Three Companies
Entering 2018 three foundries; GLOBALFOUNDRIES (GF), Samsung and TSMC were all pursuing 7nm processes and Intel was pursuing 10nm (with density similar to foundry 7nm processes). Around mid-year GF announced a “pivot” leaving only three companies pursuing the leading edge. With Intel now rumored to be exiting the foundry business there are only two foundry sources of leading-edge logic. With the exit of GF from the leading-edge, Samsung is reportedly seeing a significant increase in requests for their 7nm PDK from companies concerned about being sole sourced at TSMC.
Process Delays at Intel
In 2007 Intel introduced their 45nm process, the world’s first production process with high-K metal gates (HKMG), In 2009 Intel introduced 32nm and then in 2011 their 22nm process, the world’s first production FinFET process. 14nm was originally expected in 2013 but didn’t ramp until 2014 due to yield issues. After the 14nm delay expectations for intel reset to a 3-year cadence and 10nm was expected in 2017. Intel did ship a few 10nm parts at the end of 2017, but production is now expected to be late 2019 once again due to yield issues. Intel’s 10nm has slightly denser logic than the first-generation foundry 7nm processes and Intel is paying the price for the aggressive shrink they attempted. Both Samsung and TSMC went from 16nm/14nm to 10nm and then 7nm while Intel went from 14nm to their “10nm” process in a single step, a 2.7x density increase. There has been a lot of speculation that in order to fix the 10nm yield issues Intel will relax the density specifications, I continue to believe the process that is due to ramp up next year will have the same density previously announced (this is also what Intel is saying).
Intel is now reportedly exiting the custom foundry business. Frankly I never took Intel seriously in foundry, they have always introduced their microprocessor processes a year or more before they offered a foundry version at the same node, if they were serious about foundry the foundry process would have come out at the same time. I do not however see Intel abandoning their own internal manufacturing as some have speculated. Intel has started equipping their moth-balled Fab 42 as the lead 7nm production fab and they recently announced fab expansions in Oregon, Israel and Ireland.
Intel is currently working on 7nm due in 2020. Intel 7nm is targeted as a 2.4x shrink from their 10nm process. Based on the announcements and rumors surrounding Samsung’s 5nm process due in 2019, 4nm process in 2020 and 3nm process in 2021 and TSMC’s 5nm process due in 2019 and 3nm process forecast for around 2021, these processes will be relatively modest shrinks and we expect that if Intel achieves the target shrink their 7nm process will be as dense or denser than the foundry 3nm processes. The question is can they hit their 2020 target. Intel has commented on a conference call that they believe by introducing EUV at 7nm they think the 2.4x shrink is achievable. My concern is a 2.4x shrink will be really pushing a lot of device limits and I would not be surprised to see 7nm delayed. Even if Intel is delayed to 2021 or even 2022 they will once again have competitive density with the foundries.
A lot of people resent Intel for their many years of process leadership and perceived arrogance. Lost in this resentment is an appreciation of all the technology development Intel has driven that have become standard in the industry. I personally am concerned that Intel losing their way at the leading edge could leave a technology leadership void and I am not convinced either Samsung or TSMC are prepared to take on the role of industry technology driver.
EUV Entering Production
Samsung’s 7nm process with an estimated 7 EUV masks entered “production” mid-year and is expected to ramp up over the course of 2019. We estimate Samsung is using an average dose of 50mJ/Cm[SUP]2[/SUP] and they have announced they are not using a pellicle and achieving 1,500 wafer per day. TSMC is expected to ramp their 7FFP process with an estimated 6 EUV masks in 2019. Reports out of TSMC are that this process is ready to go. Both Samsung and TSMC are expected to enter risk production with 5nm processes in 2019 with 11 to 14 EUV masks. There is still a lot of work to do on EUV, photoresist will likely need to transition from the current chemically amplified resists (CAR) to inorganic resists, pellicles are needed, further throughput improvements and a greater understanding and mitigation of stochastics issues, but the era of EUV has clearly begun.
3D NAND Growth
Since 2014 when Samsung introduced 24-layer 3D NAND to production, we have seen 32, 48 and 64 layers enter production with 96-layers currently ramping. 3D NAND is delivering on Moore’s law with increased density and bit cost reduction. The rate of density improvement and bit cost reduction has slowed from the peak 2D NAND years but is continuing and there is a path for continued improvement into the mid to late 2020s. 2018 saw 3D NAND bit shipments exceed 2D NAND bit shipments and by 2020 some forecasters expect 3D NAND to represent 90% of all NAND bits shipped. We expect to see 128-layer 3D NAND in late 2019 or early 2020 and with string stacking there is a path all the way to 512-layers. We do see issues with bit cost beyond 384-layers with our current forecast showing an increase in bit cost beyond that number of layers, but 3D NAND offers a scaling path for many more years.
DRAM Scaling Slows
Of the three main semiconductor product groups: DRAM, Logic and, NAND, DRAM is facing the most difficult scaling path. DRAM capacitor scaling has hit a wall. DRAM capacitors must achieve an acceptable capacitance for bit retention. The capacitance depends on film thickness, film k value and capacitor area. Capacitor area has been increased by going to 3D capacitor structures, but the height of the current cylinder structures is at the mechanical limit for stability. Film thickness has been reduced as much as possible within leakage constraints. There are many options for higher k films, but leakage issues have to-date limited the options. DRAM scaling has recently focused on improving the density and performance of the peripheral circuitry. Today FinFETs and HKMG are on the horizon for further DRAM periphery improvements. DRAM capacitor – capacitance values have also been reduced to values undreamed of a few year ago. At IEDM this year Imec presented work on a new higher-k dielectric material that shows promise to break the capacitor scaling bottleneck. The new Strontium Titanate based material offers a higher-k value with acceptable leakage if the film is made thick enough. The thicker film would require a change from the current cylinder capacitor structure to a pillar structure to accommodate the increased thickness, but the potential is there for increased capacitance in the same area. This is the kind of breakthrough needed for DRAM scaling to get back on track. I plan to write more about this technology in the near future.
In spite of slower growth expected for 2019 the industry continues to move forward on technology scaling across all three major product segments. The long term outlook for the semiconductor market and underlying technologies remains strong.