I was invited to present at Nikon’s LithoVision event held the day before the SPIE Advanced Lithography Conference in San Jose. The following is a write up of the talk I gave. In this talk I discuss the three main segments in the semiconductor industry, NAND, DRAM and Logic and how technology transitions will affect lithography. Please note the slide numbering used in the article is matched to the slide numbers in the presentation.
For many years 2D NAND drove lithography with the smallest lithographic features. Recently issues with continuing to scale down 2D NAND cells has led to the switch to 3D NAND where feature sizes are relaxed, and scaling is accomplished by adding layers in the third dimension.
In slide 3 I have plotted the contact poly pitch (CPP) for 2D NAND versus time and the channel hole diameter for 3D NAND versus time. As can be seen from the figure the 3D NAND channel hole diameter is roughly 10x the size of the 2D NAND CPP. It should be noted here that the channel hole diameter is not the smallest feature on 3D NAND. 3D NAND bit lines have a 40nm pitch (the only 3D NAND multi patterned layer) but the channel hole is the most critical feature with high aspect ratio etching and filling requirements.
Slide 3. NAND critical dimension trend.
It can also be seen from Slide 3 that the channel hole diameter is getting bigger over time to manage aspect ratios.
The process of fabricating 3D NAND can be broken down into three major steps:
The mask requirements for the memory array fabrication are (see also right side of Slide 4):
- Channel mask – creates the channel hole.
- 1 stair step mask for each 8 to 10 layers. Stair step formation is done by depositing a thick photoresist mask, etching a layer, shrinking the photoresist and etching another layer until the photoresist is eroded and another mask is required. For a 64-layer device, approximately 8 stair step masks are required. There is a proposed 3 mask solution for stair step formation, but we have not seen anyone implement it yet.
- 1 or 2 slot masks depending on the product design.
- 1 via mask to contact the horizontal word line layers, the channel and the slot(s).
- Clear out masks – it isn’t possible to align through the memory array layers and clear out masks are required to etch down to the alignment marks. 2 clear out masks are typical.
As the number of memory array layers increases stress and aspect ratio issues force the memory array formation to be broken up into multiple strings. For example, for 64 layers Intel-Micron deposits 32 layers, processes the 32 layers into a memory array and then deposits another 32 layers and process them. This is called string stacking and for 2 strings the channel mask and etch occurs twice.
The bottom left of Slide 4 illustrates actual layers and forecasted layers for the four 3D NAND producers with string stacking usage. We believe Samsung is the most aggressive at continuing to use a single string approach.
Slide 4. 3D NAND Fabrication.
The adoption of CMOS under, string stacking and increasing layers all drive increasing mask counts. Slide 5 presents our forecast for mask counts for Samsung (most aggressive at avoiding string stacking) and Intel-Micron (earliest adopter of CMOS under and string stacking).
Slide 5. 3D NAND Mask Counts.
The transition to 3D has enabled NAND producers to continue the historical trend in bit density. Slide 6 presents the bit density for NAND memory die by year for the major producers including 2D and 3D NAND. Please note that both 2 bits and 3 bits per cell densities are included so that a single company may have up to two density values per year.
Slide 6. NAND Bit Density Trend.
DRAM nodes are now defined based on the smallest half-pitch on the device. For Micron Technology the Word Line is the smallest pitch and is used to define the node and for Samsung and SK Hynix the active is the smallest half-pitch and is used to define the node. Slide 7 presents the DRAM minimum pitches.
Slide 7. DRAM Minimum Pitches.
The key issue in DRAM scaling is the capacitor. A minimum capacitance value is required to reliably store a bit. The capacitance of a capacitor is given by the capacitance formula on the lower left side of slide 8. From the formula the Area of the capacitor, the k value of the dielectric film and the thickness of the dielectric film are critical parameters.
Currently the dialectic film thickness is as thin as it can be without causing unacceptable leakage.
From the graph in the bottom middle of the slide there is a trade-off between k value and band gap. Lower band gaps lead to more leakage and this trade-off has stalled the move to higher k value dielectrics. The current practice is to use nanolaminates combining aluminum oxides for low leakage and zirconium oxides for high-k values (ZAZ).
To address capacitor area without taking up too much horizonal area on a device, capacitors are fabricated in the third dimension. DRAM Capacitors are currently fabricated by forming tall thin cylinder of titanium nitride (TiN) as the capacitor bottom plate, the high-k dielectric is then deposited, and the top capacitor plate is formed covering the cylinders. The problem is the cylinders are over 1,000nm tall and only 30nm in diameter. To stabilize the cylinders silicon nitride (Si[SUB]3[/SUB]N[SUB]4[/SUB]) rings are formed half way up and at the top of the cylinder (MESH layers). Even with two MESH layers capacitor height is at the mechanical stability limit. The figure on the right side of slide 8 illustrates the TiN cylinders prior to high-k dielectric and top plate deposition.
Slide 8. DRAM Scaling Issues.
The issues described above will likely lead to an end of DRAM scaling within a few more generations. 1x DRAM (18nm) is currently in production with 1y ramping now. 1x or 1a will likely be the end of DRAM scaling. The most promising DRAM replacement is some form of MRAM but to-date the density isn’t nearly high enough. Other emerging memories generally lack the speed or endurance to replace DRAM.
Slide 9 illustrates our mask count forecast for DRAM.
Slide 9. DRAM Mask Counts.
Slide 10 illustrates the trend in DRAM bit density. When examined overall it appears that DRAM bit density is continuing the same trend line. If you look at the individual companies, it appears that they are starting to slow down.
Slide 10. DRAM Bit Density
Logic designs are assembled using standard cells. The size of a standard cell is defined by the contacted poly pitch (CPP), minimum metal pitch (MMP) and the track height. Slide 11 presents the CPP and MMP trends for the leading-edge logic producers. The CPP scales down to around 40nm and then stops due to device scaling issues that will be addressed on the next slide. MMP scales down to around 20nm although this will create metal line resistance challenges and drive the need for new interconnect materials.
Slide 11. Logic Pitch Trends.
Contacted poly pitch (CPP) is made up of the gate length plus the contact width and twice the spacer thickness (see slide 12 upper right). Gate length is limited to around 16nm for a FinFET and 13nm for a gate-all-around (GAA) horizontal nanowire (HNW) by electrostatics. Smaller contact width leads to high contact resistance and thinner spacers leads to high parasitic capacitance. The table on the lower left-hand side of slide 11 illustrates a possible CPP scaling path for TSMC and the table on the bottom right presents some experimental results.
Slide 12. Contacted Poly Pitch CPP Scaling Challenges.
As mentioned on the previous slide GAA can provide acceptable electrostatic control at shorter gate lengths than FinFETs. Nanowires provide the best electrostatics with a constrained channel surrounded by gates, but they have relatively low drive current compared to a FinFET. Horizontal nanosheets can provide better drive current than a FinFET in the same area with better than FinFET electrostatics (although not as good as HNW).
The figure in the top right of slide 13 presents the effective channel width for planar, FinFET and nanosheet devices. Higher effective channel width yields higher drive current. The figure on the bottom right compares nanowires, FinFETs and nanosheets of equal area.
Slide 13. Gate All Around (GAA).
A promising long-term scaling option for Logic is CFETs. A CFET is a horizontal stacked nanowire or nanosheet with alternating channel types. With a standard stacked nanowire or nanosheet all the layers are the same type. For a 2 deck CFET, n over p or p over n devices are fabricated. A 3-deck device is n over p over n or p over n over p. If horizontal nanosheets (HNS) are used for a 3.5nm node technology (3.1), the move to a 2-deck device provide 0.55x scaling at the same lithographic dimensions (3.2). Moving from a 3.2 – 2-deck device to a 3.3 – 3-deck devices is another 0.64x scaling. There is even work on a 14.7 device with 14nm lithographic dimensions and 3 SRAM decks and 4 logic decks. This potential solution would move logic to layer-based scaling similar to 3D NAND.
Slide 14. Logic 2D to 3D Scaling.
Slide 15 presents logic mask count trends out to a 3.2 solution. We have not yet evaluated mask counts for 3.3 and 14.7.
Slide 15. Logic Mask Count Trends
The transition of NAND from 2D to 3D has relaxed lithographic dimensions by moving to layer-based stacking. As string stacking becomes more prevalent there will be growth in mask counts.
DRAM scaling is currently limited by capacitor scaling with no long-term solution currently available. DRAM scaling will end in a few more nodes if a breakthrough isn’t found. It isn’t clear there is an emerging memory solution to replace DRAM with the required cost-performance trade-offs.
Logic scaling will likely move to horizontal stacked nanowires and nanosheets and then may transition to complimentary FETs with layer stacking analogous to 3D NAND.