WP_Term Object
(
    [term_id] => 1561
    [name] => ESD Alliance
    [slug] => esd-alliance
    [term_group] => 0
    [term_taxonomy_id] => 1561
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 99
    [filter] => raw
    [cat_ID] => 1561
    [category_count] => 99
    [category_description] => 
    [cat_name] => ESD Alliance
    [category_nicename] => esd-alliance
    [category_parent] => 386
    [is_post] => 1
)

3D: the Backup Plan

3D: the Backup Plan
by Paul McLellan on 09-05-2013 at 1:20 pm

 With the uncertainties around timing of 450mm wafers, EUV (whether it works at all and when) and new transistor architectures it is unclear whether Moore’s law as we know it is going to continue, and in particular whether the cost per transistor is going to remain economically attractive especially for consumer markets that are very price sensitive.

One of the most important alternative approaches is 3D chips based on through-silicon vias (TSVs). This is one of the focuses of Semicon Taiwan which is taking place this week. It is also a topic that Karen Savala, the president of SEMI Americas, will be talking about in her keynote at the upcoming 2013 MEPTEC Roadmaps Symposium on September 24 in Santa Clara. MEPTEC is the Microelectronics packaging and test engineering council.

Although many companies have some sort of interposer or 3D stacking technology on their roadmaps, the actual adoption for production manufacturing is slow. Gartner estimates that TSV adoption for memory will be pushed out to 2014 or 2015, with non-memory applications delayed to 2016 to 2017 if then. They currently forecast that TSV devices will account for less five percent of the units in the total wafer-level packaging market by 2017.

Part of the problem is lack of cooperation across the industry as to what technologies should be introduced when. It looks like a repeat of the 300mm wafer transition where the industry couldn’t agree when to introduce 300mm production and stop advanced development at 200mm, and they couldn’t afford to do both. As a result, there were several false starts and hundreds of millions of dollars were lost. For 450mm there are lots of consortia for collaborative R&D, probably the most important being G450C which is backed by TSMC, Intel, GlobalFoundries, Samsung and IBM and is well enough financed to have its own fab.

 For 3D-IC to be widely adopted, meaningful collaboration throughout the value chain still needs to occur. Part of the problem is that it is not even clear which parties in the value chain should be doing which steps in the manufacturing. All the players have an existing business model that must be defended or exploited based on what technical discoveries occur and what customers eventually turn out to want. It is natural that the fabless companies, foundries and OSAT houses should want to make their piece of the pie as big as possible, but without deep collaboration there won’t be a pie to divide up.

As Karen concludes:We’ll continue to see discoveries, inventions and new products in 3D-IC and progress will continue. Hundreds of patents in the area have already been issued. We’re seeing innovation and invention in wafer bonding, via manufacturing, and other areas. Standards work at JEDEC and SEMI will also contribute to the market’s development, both to enable processes and cost-reduce manufacturing, but without the emergence of a new, robust collaboration model that can deliver meaningful agreements between key constituencies, the promise of 3D innovation will remain distant and illusive.

Karen’s thoughts on 3D collaboration are online here. Details of the 2013 MEPTEC Roadmaps Symposium are here.


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