SEMICON Taiwan is September 3rd to 6th in TWTC Nangang Exhibition Hall. Just as with Semicon West in July in San Francisco, there is lots going on. But one special focus is 3D IC. There is a 3DIC and substrate pavilion on the exhibit floor and an Advanced Packaging Symposium. Design tools, manufacturing, packaging and testing solutions for 2.5D-IC process are available this year, and the most important issue is how to improve its throughput to enable 2.5D-IC mass production in 2014.
3DIC is one of the key “More Than Moore” technologies to increase system capability in ways other than technology scaling (28nm, 20, 14/16 etc). Although in the long-term true 3D systems may be designed, with logic on all the layers, in the shorter term there are two particular areas showing promise:
- 3D memories, stacking memory die, either to put them into a package like with Micron’s memory cube, or to stack memory on top of logic, probably using JEDEC’s wide IO standard
- 2.5D interposer designs, where various chips, probably from different technologies, are flipped and attached to a silicon (or perhaps glass) interposer
Although there are some design issues with both of these, pipe-cleaner designs have successfully been done so the real roadblocks are economic.
The first economic problem is called the known-good-die problem. With a single die in a package, if a bad die slips through wafer test and gets packaged, then fails final test then you have wasted the cost of the package, the cost of putting one die in a package and bonding it out. You didn’t waste the die, it was bad anyway. Since wafer test costs money, there is a crossover point where doing more testing at the wafer stage outweigh the cost of discarding the occasional package. With a 2.5D interposer based design, a bad die that slips through means you waste a very expensive package, an interposer and all the other die in the package which were good, plus all the cost of putting everything together. It really is a lot more important that bad die do not survive that long and so the economics of wafer sort change completely.
The second economic problem is the cost of the assembly process. Wafers need to be thinned, glued to something strong enough that it can be handled, bumped, cut up, the backing removed, the die put in the package, the bumps bonded etc. If this is too expensive then it makes the whole idea of using a silicon interposer unattractive versus just using separate packages or doing some sort of multi-die bonded package.
Taiwan is ground zero of the packaging and assembly world. It has the world’s largest packaging and testing company, ASE, as well as SPIL, PTI, and ChipMOS reaching a global packaging and testing foundry market share of over 50 percent. Amkor (Korea) and STATS ChipPAC (Singapore) have also set up plants in Taiwan.
Design tools, manufacturing, packaging and testing solutions for 2.5D-IC process are available this year. So the technology is there. The most important issue is how to improve throughput to enable 2.5D-IC mass production in 2014.