Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design StrategyThe TSMC Technology Symposium recently kicked off in…Read More
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Beyond the Memory Wall: Unleashing Bandwidth and Crushing LatencyVSORA AI Processor Raises $46 Million to Fast-Track…Read More
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AI has changed a lot in the last ten years. In 2012, convolutional neural networks (CNNs) were the state of the art for computer vision. Then around 2020 vison transformers (ViTs) redefined machine learning. Now, Vision-Language Models (VLMs) are changing the game again—blending image and text understanding to power everything… Read More
Jonathan Klamkin, Ph.D. is founder and CEO of Aeluma, Inc. (ALMU). He is a Professor at the University of California Santa Barbara and has previously worked at Boston University, Scuola Superiore Sant’Anna, MIT Lincoln Laboratory, and BinOptics Corp. (a laser diode manufacturer that was acquired by Macom in 2015). He is the recipient… Read More
We have talked about metamorphic testing before. Here is a clever application to testing an AMS subsystem. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.… Read More
In part one of this webinar series, Keysight and Modelithics looked at the use of 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation of high-frequency RF board designs. Part two continues the exploration of RF board design flows for simulating active circuits on boards, again… Read More
Ceva recently unveiled its XC21 and XC23 DSP cores, designed to revolutionize wireless communications and edge AI processing. These new offerings build upon the Ceva-XC20 architecture, delivering unmatched efficiency, scalability, and performance for 5G-Advanced, pre-6G, and smart edge applications. As demand grows … Read More
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For advanced semiconductor designs, achieving both design rule check clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. Balancing electrical performance and layout integrity is a difficult task. Achieving an optimal… Read More
Dan is joined by Nick Kepler, COO and Director at Silicon Catalyst. Nick has over 30 years of experience in the semiconductor industry, with varied leadership and technology management roles including semiconductor process technology development and manufacturing, design enablement, technical program management, and … Read More
Jonas Sundqvist received his PhD in inorganic chemistry from Uppsala University, Department for Materials Chemistry at The Ångström Laboratory in 2003 where he developed ALD and CVD processes for metal oxide ALD and CVD processes using metal iodides. Jonas is in charge of the daily business at AlixLabs – as a co-founder, he’s… Read More
How much perfectly good silicon is being discarded in the quest for reliability? During high-volume chip manufacturing, aggressive testing with strict thresholds may ensure quality but reduces yield, discarding marginal chips that could function flawlessly. On the other hand, prioritizing yield risks allowing defective… Read More
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