Tessent MemoryBIST Expands to Include NVRAMThe concept of built-in self-test for electronics has…Read More
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Smart Verification for Complex UCIe Multi-Die ArchitecturesBy Ujjwal Negi - Siemens EDA Multi-die architectures…Read More
Transistor fabrication has spanned the gamut from planar devices o FinFET to Gate-All-Around (GAA) as silicon dimensions have decreased in the quest for higher density, faster speeds and lower power. Process development engineers use powerful simulation tools to predict and even optimize transistor performance for GAA devices.… Read More
A century ago, 391 San Antonio Road in Mountain View, California, housed an apricot-packing shed. Today, it’s marked by sculptures of diodes and a transistor, commemorating the 1956 founding of Shockley Semiconductor Laboratory—the birthplace of Silicon Valley. William Shockley, co-inventor of the transistor, aimed… Read More
In chiplet-based design we continue the march of Moore’s Law by scaling what we can put in a semiconductor package beyond the boundaries of what we can build on a single die. This style is already gaining traction in AI applications, high performance computing, and automotive, each of which aims to scale out to highly integrated … Read More
The Future Horizons Industry Update Webinar, presented today by Malcolm Penn, provides a comprehensive analysis of the semiconductor industry’s current state and future trajectory. Founded in 1989, Future Horizons leverages over 300 man-years of experience, emphasizing impartial insights from facts (e.g., IMF … Read More
Digital design engineers have used DFT automation technologies like scan and ATPG for decades now, however, analog blocks embedded within SoCs have historically required that a test engineer write tests that require specialized expertise and that can take man-months to debug. Siemens has a long history in the DFT field, SPICE… Read More
MediaTek’s first chipset using 2nm technology expected in late 2026
MediaTek, a global leader in fabless semiconductor design, has announced a groundbreaking achievement in its partnership with TSMC. The company has successfully developed a flagship system-on-chip (SoC) utilizing TSMC’s cutting-edge 2nm process technology,… Read More
In the rapidly evolving landscape of semiconductor manufacturing, the demand for processors that handle increasing workloads while maintaining power efficiency and compact form factors has never been higher. Intel’s Foveros 2.5D packaging technology emerges as a pivotal innovation, enabling denser die integration… Read More
While stochastic defects link yield with the practical resolution of EUV lithography resulting from its quantum nature [1], very low yields of EUV processes are more readily linked to the use of EUV masks without pellicles. Pellicles are thin film membrane covers on masks (regardless of wavelength: EUV and DUV and i-line) used… Read More
Dan is joined by Ross Miller, senior vice president at SkyWater Technology. Ross leads the industrial and aerospace businesses while steering the company’s branding, and corporate communications efforts. He is a seasoned semiconductor and technology executive with over 20 years of experience across startup, enterprise,… Read More
In the fast-paced semiconductor industry Synopsys has redefined EDA with its Synopsys.ai Copilot, a generative AI tool. Since its launch in November 2023, and yes I was at the launch and very skeptical, Copilot has evolved to address the industry’s growing design complexity and projected 15-30% workforce gap by 2030. Let’s… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet