JUN YUAN BIO
◆Engineer for chip design, simulation, and P&R at AMD; Senior Engineer for chip verification (emulation, equivalence checking, formal verification) at Motorola since 1992.
◆Held R&D and technical management roles in formal verification EDA at Verplex, Jasper, and Cadence since 2003.
◆Founded Arcas-tech… Read More
CTO Interview with Taylor Barton of Certus SemiconductorTaylor Barton is a Lead Analog/Mixed-Signal and I/O…Read More
Generating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity By Defacto Staff Today’s chips are no longer…Read More
Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in ComputingThe Global Semiconductor Alliance will present Micron Technology…Read More
NIST Sets a Clearer Course for the Post-Quantum Security TransitionNIST’s report, Transition to Post-Quantum Cryptography Standards, gives…Read MoreCEO Interview with Pratap Ranade of Arena Physica
Pratap Ranade is CEO and Co-Founder of Arena Physica. Pratap first trained as a physicist at Stanford and Columbia before joining McKinsey as an Associate Partner advising tech and semiconductor companies. He then founded Kimono Labs, backed by Sam Altman, Peter Thiel and Y-Combinator, which was acquired by Palantir. There,… Read More
Podcast EP377: Aion Silicon’s Growth and Impact Across Multiple Markets with Oliver Jones
Daniel is joined by Oliver Jones, CEO of Aion Silicon, a global semiconductor design and engineering company delivering custom silicon solutions for the AI age. He leads the company’s strategy and growth as it continuously helps technology companies bring advanced SoC designs to market from architecture through production,… Read More
ChipNexus Brings Agentic AI into Established Analog Design Flows
ChipNexus has introduced its NEX Analog Agent, bringing conversational automation to analog engineering workflows built around Cadence Virtuoso, Spectre simulation and Siemens Calibre physical verification. Available now, the software operates with customers’ installed tools, licenses and process design kits, giving… Read More
Delivering Silicon Systems Through AI Disruption, Part 2: The Conductor
Conductor: the person who keeps every section of the orchestra in time without playing an instrument. In this article, it’s your operating model.
In Part 1, I wrote about the score, your designed workflows across the three layers Gene Kim and Steven Spear describe in Wiring the Winning Organization: the technical work, … Read More
WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUs
Modern AI models are opening up new possibilities at the edge. Turning those possibilities into responsive, efficient applications, however, requires more than choosing hardware with an impressive TOPS figure. Developers need to understand how models behave on their target devices, where performance is lost, and which optimisations… Read More
Interview with David Tester VP of Engineering Mach42
David Tester is the VP of Engineering at Mach42, with 30 years of experience in semiconductor development, engineering leadership, and business growth. As Chief Engineer at EnSilica, he helped transform the company from a design consultancy into a publicly listed fabless semiconductor business, scaling the organisation … Read More
Glass Is Becoming an AI Infrastructure Platform
The value of glass will be determined not by its material properties alone, but by whether it can expand the package architecture window and be realized repeatedly at manufacturing scale.
AI infrastructure is pushing advanced packaging into a regime where the substrate itself increasingly determines what can be built.
As packages… Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
The philosophy of relying on a single, unified IP stack to lower your total cost of ownership is not a new concept invented just for the AI era. Semiconductor engineering teams have been weighing the trade-offs of piecemeal versus integrated intellectual property sourcing for decades. In previous process generations, veering… Read More
CTO Interview with Taylor Barton of Certus Semiconductor
Taylor Barton is a Lead Analog/Mixed-Signal and I/O IC Design Engineer at Certus Semiconductor, where he has worked since December 2022. He has designed more than 20 silicon-proven I/O and ESD libraries and has led analog and I/O IP projects, including ADC and SerDes designs. Taylor holds B.S. and M.S. degrees in Electrical Engineering… Read More


The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival