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Semiconductor Expert Forum

Video EP3: A Discussion of Challenges and Strategies for Heterogeneous 3D Integration with Anna Fontanelli

Video EP3: A Discussion of Challenges and Strategies for Heterogeneous 3D Integration with Anna Fontanelli
by Daniel Nenni on 05-02-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by Anna Fontanelli, founder and CEO of MZ Technologies. Anna explains some of the substantial challenges associated with heterogeneous 3D integration. Dan then begins to explore some of the capabilities of GenioEVO, the first integrated chiplet/package… Read More

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CEO Interview with Richard Hegberg of Caspia Technologies

CEO Interview with Richard Hegberg of Caspia Technologies
by Daniel Nenni on 05-02-2025 at 6:00 am
Categories: Caspia Technologies, CEO Interviews, Security

Richard Hegberg

Rick has a long and diverse career in the semiconductor industry. He began as VP of sales at Lucent Microelectronics. He has held executive roles at several high-profile companies and participated in several acquisitions along the way. These include NetApp, SanDisk/WD, Atheros/Qualcomm, Numonyx/Micron, ATI/AMD, and VLSI… Read More

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TSMC Describes Technology Innovation Beyond A14

TSMC Describes Technology Innovation Beyond A14
by Mike Gianfagna on 05-01-2025 at 10:00 am
Categories: Events, Foundries, TSMC
2 Comments

Device Architecture Outlook

The inaugural event for the 2025 TSMC Technology Symposium recently concluded in Santa Clara, California. This will be followed by events around the world over the next two months. We have summarized information from this event regarding process technology innovation and advanced packaging innovation. Overall, the A14 process… Read More

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SNUG 2025: A Watershed Moment for EDA – Part 2

SNUG 2025: A Watershed Moment for EDA – Part 2
by Lauro Rizzatti on 05-01-2025 at 6:00 am
Categories: EDA, Events, Synopsys

SNUG 2025 Scaling Compute for the Age of Intelligence Figure 1

At this year’s SNUG (Synopsys Users Group) conference, Richard Ho, Head of Hardware, OpenAI, delivered the second keynote, titled “Scaling Compute for the Age of Intelligence.” In his presentation, Richard guided the audience through the transformative trends and implications of the intelligence era now unfolding before… Read More

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Emerging NVM Technologies: ReRAM Gains Visibility in 2024 Industry Survey

Emerging NVM Technologies: ReRAM Gains Visibility in 2024 Industry Survey
by Daniel Nenni on 04-30-2025 at 11:00 am
Categories: IP
4 Comments

Slide1

A recent survey of more than 120 anonymous semiconductor professionals offers a grounded view of how the industry is evaluating non-volatile memory (NVM) technologies—and where things may be heading next.

The 2024 NVM Survey, run in late 2024 and promoted through various semiconductor-related platforms and portals including… Read More

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Feeding the Beast: The Real Cost of Speculative Execution in AI Data Centers

Feeding the Beast: The Real Cost of Speculative Execution in AI Data Centers
by Jonah McLeod on 04-30-2025 at 10:00 am
Categories: AI

Per Module Cost Breakdown RISCV

For decades, speculative execution was a brilliant solution to a fundamental bottleneck: CPUs were fast, but memory access was slow. Rather than wait idly, processors guessed the next instruction or data fetch and executed it ‘just in case.’ Speculative execution traces its lineage back to Robert Tomasulo’s work… Read More

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LLMs Raise Game in Assertion Gen. Innovation in Verification

LLMs Raise Game in Assertion Gen. Innovation in Verification
by Bernard Murphy on 04-30-2025 at 6:00 am
Categories: AI, Cadence, EDA

Innovation New

LLMs are already simplifying assertion generation but still depend on human-generated natural language prompts. Can LLMs go further, drawing semantic guidance from the RTL and domain-specific training? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO… Read More

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Automotive Functional Safety (FuSa) Challenges

Automotive Functional Safety (FuSa) Challenges
by Daniel Payne on 04-29-2025 at 10:00 am
Categories: EDA, Synopsys

silicon lifecycle management slm diagram min

Modern vehicles have become quite sophisticated, like a supercomputer on wheels. They integrate a vast number of electronic components, including thousands of chips, to deliver advanced functionalities ranging from infotainment to critical safety systems. This increasing complexity necessitates a robust approach to … Read More

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Scaling AI Infrastructure with Next-Gen Interconnects

Scaling AI Infrastructure with Next-Gen Interconnects
by Kalar Rajendiran on 04-29-2025 at 6:00 am
Categories: 3D IC, AI, Chiplet, EDA, IP, Synopsys

Data Centers Reimagined for Future of Gen AI

At the recent IPSoC Conference in Silicon Valley, Aparna Tarde gave a talk on the importance of Next-Gen Interconnects to scale AI infrastructure. Aparna is a Sr. Technical Product Manager at Synopsys. A synthesis of the salient points from her talk follows.

The rapid advancement of artificial intelligence (AI) is fundamentally… Read More

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Siemens Describes its System-Level Prototyping and Planning Cockpit

Siemens Describes its System-Level Prototyping and Planning Cockpit
by Mike Gianfagna on 04-28-2025 at 10:00 am
Categories: 3D IC, AI, EDA, Siemens EDA

Siemens Describes its System Level Prototyping and Planning Cockpit

We all know semiconductor design is getting harder. Much harder when you consider the demands of AI workloads and heterogeneous integration of many chiplets in a single package. This class of system demands co-optimization across the entire design flow. For example, functional verification, thermal analysis, signal and power… Read More