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Semiconductor Expert Forum

Podcast EP306: The Challenges of Advanced AI Data Center Design with Josue Navarro

Podcast EP306: The Challenges of Advanced AI Data Center Design with Josue Navarro
by Daniel Nenni on 09-05-2025 at 10:00 am
Categories: General

Dan is joined by Josue Navarro, product marketing engineer for Microchip’s dsPIC business unit. He began his career as a process engineer at Intel and has since transitioned into product marketing with Microchip Technology where he supports customers developing system designs utilizing Microchip’s Digital Signal … Read More

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Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business

Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business
by Admin on 09-05-2025 at 8:00 am
Categories: Cadence, EDA

Cadence Hexagon

In a bold move that underscores the accelerating convergence of electronic design automation (EDA) and mechanical engineering, Cadence Design Systems announced its agreement to acquire Hexagon AB’s Design & Engineering (D&E) business for approximately €2.7 billion, equivalent to about $3.16 billion. This… Read More

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TSMC 2025 Update: Riding the AI Wave Amid Global Expansion

TSMC 2025 Update: Riding the AI Wave Amid Global Expansion
by Daniel Nenni on 09-05-2025 at 6:00 am
Categories: 3D IC, AI, Events, Foundries, TSMC

CC Wei Donold Trump Handshake

Welcome to the second half of a very exciting year in semiconductors. While Intel and Samsung Foundry have made quite a few headlines, TSMC continues to execute flawlessly at 3nm and 2nm. With the TSMC OIP Ecosystem Forums starting later this month let’s take a look at how we got to where we are today.

The TSMC OIP Ecosystem Forum… Read More

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Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation

Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation
by Daniel Nenni on 09-04-2025 at 10:00 am
Categories: 3D IC, Alchip, Chiplet, Semiconductor Services

Alchip 3D IC Test Chip TSMC N2

Today Alchip Technologies, a Taipei-based leader in high-performance and AI computing ASICs, announced a significant milestone with the successful tape-out of its 3D IC test chip. This achievement not only validates Alchip’s advanced 3D IC ecosystem but also positions the company as a frontrunner in the rapidly evolving field… Read More

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WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design

WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
by Daniel Nenni on 09-04-2025 at 8:00 am
Categories: Easy-Logic, EDA, Events

Blog image

This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.

The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More

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Beyond Von Neumann: Toward a Unified Deterministic Architecture

Beyond Von Neumann: Toward a Unified Deterministic Architecture
by Admin on 09-04-2025 at 6:00 am
Categories: IP, RISC-V

Beyond Von Neumann

By Thang Tran

For more than half a century, the foundations of computing have stood on a single architecture: the Von Neumann or Harvard model. Nearly all modern chips—CPUs, GPUs, and even many specialized accelerators—rely on some variant of this design. Over time, the industry has layered on complexity and specialization to… Read More

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Intel Unveils Clearwater Forest: Power-Efficient Xeon for the Next Generation of Data Centers

Intel Unveils Clearwater Forest: Power-Efficient Xeon for the Next Generation of Data Centers
by Kalar Rajendiran on 09-03-2025 at 10:00 am
Categories: 3D IC, Chiplet, Foundries, Intel Foundry

Hot Chips Logo 2025

At the recent Hot Chips conference, Intel® unveiled Clearwater Forest, its next-generation Xeon® 6 processor with efficiency cores (E-cores). The unveiling was made by Don Soltis, Xeon Processor Architect and Intel Fellow with over four decades of processor design experience and a long-standing contributor to the Xeon roadmap.… Read More

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EUV Resist Degradation with Outgassing at Higher Doses

EUV Resist Degradation with Outgassing at Higher Doses
by Fred Chen on 09-03-2025 at 8:00 am
Categories: Lithography

EUV Resist Degradation with Outgassing at Higher Doses

Dosing for EUV lithography walks a fine line between productivity and defectivity. Fabs can choose higher-dose exposures to suppress photon shot noise [1]. However, higher doses require EUV machines to scan the wafer at slower speeds, degrading throughput [2].

On the other hand, there is the threat of resist thickness loss that… Read More

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Two Perspectives on Automated Code Generation

Two Perspectives on Automated Code Generation
by Bernard Murphy on 09-03-2025 at 6:00 am
Categories: AI

pair programming

In engineering development, automated code generation as a pair programming assistant is high on the list of targets for GenAI applications. For hardware design obvious targets would be to autogenerate custom RTL functions or variants on standard functions, or to complete RTL snippets as an aid to human-driven code generation.… Read More

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Intel’s IPU E2200: Redefining Data Center Infrastructure

Intel’s IPU E2200: Redefining Data Center Infrastructure
by Kalar Rajendiran on 09-02-2025 at 10:00 am
Categories: AI, Foundries, Intel Foundry

Hot Chips Logo 2025

We are in the midst of one of the most transformative periods for data center infrastructure. The explosion of AI, cloud-scale workloads, and hyperscale networking is forcing rapid innovation not only in compute and storage, but in the very fabric that connects them. At the recent Hot Chips conference, Pat Fleming gave a talk on… Read More