AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk Architecting Smarter SoCs with…Read More
AI-native Virtual Chiplet Eco-systems: Shift Left, Shift Up, and Shift Out to accelerate Chiplet adoptionSystems-in-package (SIPs) with 2.5D and 3D heterogenous integration,…Read More
The Yield Partnership: Intel and PDF Solutions Tackle Advanced NodesOne of the most difficult things to do…Read More
Webinar: Faster Design Spec to Implementation using IP-XACTAs SoC design flows grow increasingly complex, IP-XACT…Read More
Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late Chip-level vulnerability is becoming an existential threat…Read More
There have been a lot of interesting announcements and presentations lately from the leading edge foundries. Looking at all of this information, a pretty interesting picture begins to emerge.
TSMC
TSMC is far and away the world’s largest foundry. In their 2014-Q2 conference call TSMC outlined their expectations for the balance… Read More
At SEMICON West two weeks ago, Bob Johnson of Gartner presented the outlook for the semiconductor market, semiconductor capital spending, and wafer fab equipment spending. Thanks to Daniel Nenni for providing the link to the SEMI/Gartner Market Symposium presentations at https://sites.google.com/a/semi.org/market-symposium/home/speaker-presentations… Read More
There is never enough memory bandwidth. Well, occasionally there is but many SoCs have lots of blocks that communicate through memory, typically off-chip DRAM. In 2001 Sonics created their first solution to this problem with MemMax technology that was incorporated into their SonicsSX product. This has been used in over 100 designs… Read More
Cadence announced their 2Q results this afternoon. I listened to the conference call.
You can read all the details of the results in the press release but the big picture is:
While listening to the Intel and AMD conference calls last week I was reminded of the ATI acquisition by AMD and the painfully long cultural assimilation that ensued. The title of this blog could just as easily have been “Custom vs Synthesizable Design Cultures” or “The Real Reason Why AMD is Fabless” because that is closer to how … Read More
The reliability metric, Mean Time Between Failures (MTBF), is often misunderstood. Use of an MTBF metric generally assumes a random failure process, one that is very infrequent and has no memory of past failures. Such failure modes can occur in System-on-Chip (SoC) designs and include radiation effects, synchronizer malfunctions… Read More
I recently published an article on Semiwiki “Is SOI Really Less Expensive”. That article was the result of months of careful research and analysis. I looked at planar FDSOI versus bulk planar, bulk FinFETs and FinFETs on SOI at three different nodes. I took a consistent set of assumptions with respect to the fab used to run the processes,… Read More
FPGAs in many ways are still a bit mysterious to some folk. I was at a high level summit in April, and I realized that many there had no idea what an FPGA was. They knew at least what a CPU was or meant and that their kids talk about GPUs. A good analogy I have for an FPGA when compared to a CPU is something like this. Think of the FPGA and CPU as … Read More
Rather than watch the World Cup battle for third place, my beautiful wife and I spent last Saturday afternoon at the CASPA Wearables Symposium. The most interesting presentation was from Samsung because it included slides on their foundry offering. In regards to wearables, I still don’t see the ROI I need to buy one, yet. We are getting… Read More
I spent all of last week at SEMICON West meeting with customers, potential customers, partners and various industry analysts and experts. I was involved in many interesting discussions over the course of the week and I thought I would share some of the more interesting observations:
Alternate Fin Materials Pushed Out
I have for… Read More
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Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?