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CMOS 2.0 is Advancing Semiconductor Scaling

CMOS 2.0 is Advancing Semiconductor Scaling
by Daniel Nenni on 10-19-2025 at 10:00 am

CMOS 2.0

In the rapidly evolving landscape of semiconductor technology, imec’s recent breakthroughs in wafer-to-wafer hybrid bonding and backside connectivity are paving the way for CMOS 2.0, a paradigm shift in chip design. Introduced in 2024, CMOS 2.0 addresses the limitations of traditional CMOS scaling by partitioning… Read More


CEO Interview with Dr. Bernie Malouin Founder of JetCool and VP of Flex Liquid Cooling

CEO Interview with Dr. Bernie Malouin Founder of JetCool and VP of Flex Liquid Cooling
by Daniel Nenni on 10-19-2025 at 8:00 am

Bernie Malouin Headshot JetCool

Bernie Malouin is a technical professional with demonstrated experience from concept studies through system deployment. He has a strong track record working in dynamic environments, from highly complex, multi-million dollar development programs to deeply technical research projects.

He founded JetCool Technologies… Read More


Podcast EP311: An Overview of how Keysom Optimizes Embedded Applications with Dr. Luca TESTA

Podcast EP311: An Overview of how Keysom Optimizes Embedded Applications with Dr. Luca TESTA
by Daniel Nenni on 10-17-2025 at 10:00 am

Daniel is joined by Luca TESTA, the COO and co-founder of Keysom. After studying microelectronics in Italy, Luca obtained his PhD in France while working with STMicroelectronics on analog/RF circuit design.

Dan explores the charter and focus of Keysom with Luca. Luca describes how Keysom is providing an automated and reliable… Read More


Webinar – The Path to Smaller, Denser, and Faster with CPX, Samtec’s Co-Packaged Copper and Optics

Webinar – The Path to Smaller, Denser, and Faster with CPX, Samtec’s Co-Packaged Copper and Optics
by Mike Gianfagna on 10-17-2025 at 6:00 am

Webinar – The Path to Smaller, Denser, and Faster with CPX, Samtec’s Co Packaged Copper and Optics

For markets such as data center, high-performance computing, networking and AI accelerators the battle cry is often “copper is dead”. The tremendous demands for performance and power efficiency often lead to this conclusion. As is the case with many technology topics, things are not always the way they seem. It turns out a lot … Read More


Webinar – IP Design Considerations for Real-Time Edge AI Systems

Webinar – IP Design Considerations for Real-Time Edge AI Systems
by Mike Gianfagna on 10-16-2025 at 10:00 am

Webinar – IP Design Considerations for Real Time Edge AI Systems

It is well-known that semiconductor growth is driven by AI. That simple statement breaks down into many complex use cases, each with its own requirements and challenges. A webinar will be presented by Synopsys on October 23 that focuses on the specific requirements for one of the most popular use cases – AI at the edge. The speaker… Read More


WEBINAR: Design and Stability Analysis of GaN Power Amplifiers using Advanced Simulation Tools

WEBINAR: Design and Stability Analysis of GaN Power Amplifiers using Advanced Simulation Tools
by Daniel Nenni on 10-16-2025 at 6:00 am

figure1

Why should high frequency circuit designers consider stability early in the design process? Isn’t there enough to worry about just making the circuit function at the fundamental frequency?

In the past, Microwave Engineers used to solve stability problems in the lab, perhaps adding bypassing or loss in a strategic location to… Read More


Visualizing hidden parasitic effects in advanced IC design 

Visualizing hidden parasitic effects in advanced IC design 
by Admin on 10-15-2025 at 10:00 am

[white paper] Parasitic Analysis Figures

By Omar Elabd

As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More


Statically Verifying RTL Connectivity with Synopsys

Statically Verifying RTL Connectivity with Synopsys
by Bernard Murphy on 10-15-2025 at 6:00 am

TestMAX Advisor Use Model min

Many years ago, not long after we first launched SpyGlass, I was looking around for new areas where we could apply static verification methods and was fortunate to meet Ralph Marlett, a guy (now friend) with extensive experience in DFT. Ralph joined us and went on to build the very capable SpyGlass DFT app. So capable that SpyGlass… Read More


Assertion IP (AIP) for Improved Design Verification

Assertion IP (AIP) for Improved Design Verification
by Daniel Payne on 10-14-2025 at 10:00 am

Detailed flow min

Over the years design reuse methodology created a market for Semiconductor IP (SIP), now with formal techniques there’s a need for Assertion IP (AIP). Where each AIP is a reusable and configurable verification component used in hardware design to detect protocol and functional violations in a Design Under Test (DUT).  LUBIS … Read More


Secure-IC and Silicon Labs Raise the Bar for Hardware Security

Secure-IC and Silicon Labs Raise the Bar for Hardware Security
by Mike Gianfagna on 10-14-2025 at 8:00 am

Secure IC and Silicon Labs Raise the Bar for Hardware Security

Cybersecurity is getting more critical every day. Thanks to sophisticated AI attacks, the need for hardware chip-level security is greater than ever. To fortify hardware against these types of attacks is not easy. There are three key attributes of a successful strategy: a well-designed root-of-trust, collaboration to ensure… Read More