PowerArtist RTL Power Estimation Folds into KeysightBack in the late 1990s, Sente launched a…Read More
Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026At the 2026 VLSI Symposium, Intel Foundry provided…Read More
GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneckAs semiconductor manufacturing pushes toward advanced nodes with…Read More
A tower-like heterogeneous packaging architecture for the AI era VEMC: The Vertical System…Read More
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The periodic table shows that Silicon (Si) is in a column along with other elements like Carbon (C) and Germanium (Ge). With so much emphasis on Silicon, you’d think that the other semiconductor materials have been neglected a bit.
Silicon is a wonderful material and most of our consumer electronics and handheld devices … Read More
Next week, eSilicon are kicking off a very widespread survey to measure some important semiconductor design and manufacturing challenges. Their goal is to measure customer sentiment regarding how Big Data, the Cloud and the Internet can impact these challenges. But here’s a secret, the survey is already live and you can… Read More
In the face of shrinking time-to-market windows, semiconductor companies are aggressively vying with each other to emerge with new or variants of existing ICs and SoCs to gain market share. The growth of the mobile market –wireless, networking, storage, and computing – as well as new areas such as the Internet of things (IoT) and… Read More
In college many of us dreamed of starting up our own company by offering something new that has never been done before. Today I spoke by phone with Yunshan Zhuin Shanghai, and he has actually lived out this scenario by founding NextOp in 2006, then getting that company acquired by Atrentain 2012. The new capability that NextOp created… Read More
RTL designers know that their code gets transformed into gates and cells by using a logic synthesis tool, however these gates and cells are further comprised of transistors and sometimes you really need to optimize the transistor sizing to reach power, performance and area goals. I’ve done transistor-level IC design before,… Read More
IC designers have been running analysis tools for power, noise and reliability for many years now, so what is new when you start using FinFET transistors instead of planar transistors? Calvin Chow from ANSYS (Apache Design) presented on this topic earlier in the summer through a 33 minutewebinar that has been archived. There is… Read More
Next week Mike Jensen of Mentor will present a webinar Improving Complex System Design Reliability and Robustness. The webinar will be presented live twice and presumably available for replay soon after, as is usually the case:
Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, or more accurately the SoC variant combining ARM cores with programmable… Read More
For several years now, TSMC has run increasingly sophisticated IP validation. Ramping a new process as a foundry requires a number of things to all come together almost simultaneously: the process, of course, and some designs to run and start to recover the huge capital investment a modern fab entails. With many SoCs having over… Read More
Coke with no ice. You see I am not cheap, or even frugal but a good steward. One of the things that I hate the most is waste. You know lights on in every room, door open during winter and driving 25 miles to save a dollar on gas.
One will notice fairly quickly that with Xilinx UltraScale 20nm FPGAs coupled with the new-fangled analytical … Read More
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