Cadence announced their Q4 and 2014 results yesterday. They are the only one of the big 3 EDA companies whose fiscal year is the calendar year so Synopsys and Mentor will not be joining them in announcing them this week.
I won’t go into the numbers in detail, you can find them all easily enough. But it is a pity that statements like this can’t be backed up with the company names:We had over 10 full flow digital wins in 2014. We also had segment share gains at several leading customers, including a global marquee company and most recently at a major fables semiconductor company.
Lip-Bu said that Tempus/Voltus/Quantus had more than 50 tapeouts which is impressive considering how new these products are. Of course it is possible for Synopsys to claim the same tapeouts, perhaps. I’ll bet risk-averse design groups (that would be all of them) run PrimeTime as well as Tempus, for example.
Palladium emulation seems to be doing well. This is a particularly sensitive area since margins on a product like Palladium are lower than a pure software product and the market has recently become very competitive. For once we have a name, and a good one, in that MediaTek doubled their Palladium capacity last quarter. Cadence have their next generation emulation (presumably still called Palladium) which is shipping in the second half of this year. In the questions it was admitted that the product was late (“took a bit longer”) but that it will have higher margins than the current product line.
IP grew 40% in 2014 vs 2013, led by DDR (the outgrowth of the Denali acquisition) including by HiSilicon earlier in the year with the world’s first 16FF tapeout. Tensilica had the largest number of new licenses ever last quarter and also passed the 2B cores/year run-rate in production. Then in the questions it is clear Cadence is having some major success at 10nm in IP too:In the most advanced 10-nanometer we won and in fact the largest IP contract to-date and with one of our largest top customer.
You might remember that the Virtuoso product line got split into the original version for mature nodes and Virtuoso for advanced nodes used for 20nm and below (with support for double patterning, FinFET etc). Over 40 customers are using the advanced node version.
For a number of reasons, Palladium just being one of them, margins were guided down in the first half of next year. Other factors called out in the questions: social security payments run in the first half of the year until they meet the cap; vacation is mostly taken in the second half of the year. They also said that margins are under pressure from their investment in technology and in customer support for their major new customer wins. They are forecasting a 6% top line growth for 2015, slightly faster than the overall EDA industry and faster than the world economy.
Lip-Bu was asked about the extra investment and margins and would margins expand in the future as the investment started to earn a return. Lip-Bu gave one of his inscrutable answers which is not clear whether the answer is yes or no:First of all, I think the investments are highly leveragable across customers. That will provide the leadership and market share as a key driver for success for our business going forward. And I am confident if we execute and then successful in the long-term and are proliferating our product more in the winning customer, marquee customer and also the next level of customer will be also embraced, that in the end, it will benefit in our shareholders.
Another interesting comment in the questions was about 10nm being a long lived node:clearly the 10-nanometer, the main reason as it is going to be a long node because 7 and 5 is unclear and EUV timing is unclear.
SeekingAlpha transcript of the call is here.Share this post via: