CEO Interview with Dr. Sean Wei of Easy-Logic

Dr. Wei has served as CEO of Easy-Logic since 2020, focusing on building a strong operational foundation for the company. Previously, as CTO, he led the development of the core algorithms and tool architecture for the flagship product EasylogicECO, seamlessly aligning EasylogicECO technology with user needs.

Dr. Wei holds a PhD in Computer Engineering from The Chinese University of Hong Kong and an MSc and BSc in Computer Science and Technology from Tsinghua University.

Tell us about your company?

Easy-Logic Technology is a specialist provider of Functional ECO solutions, founded in Hong Kong in 2013. Our core team grew out of the EDA laboratory at The Chinese University of Hong Kong, and our core algorithms won first place in the CAD Contest at ICCAD for three consecutive years (2012–2014).

Building on this research, we develop industrial-grade EDA software. Our Functional ECO technology enables a breakthrough incremental design flow for the ASIC industry. We now serve nearly 100 paying customers, including leading semiconductor design companies in mainland China, Taiwan, the United States, and South Korea.

What problems are you solving?

We address late-stage logic and functional changes in chip design—known as Functional ECO. Industry data indicates that over 86% of ASICs require two or more tape-outs, with logic and functional issues among the leading causes of tape-out failure.

ASIC development involves complex stages such as logic synthesis, DFT, and placement&routing. Unexpected bugs, specification changes, or evolving customer requirements can necessitate functional changes late in the process, and re-running the entire design flow can take months and cost millions of dollars. The key challenge is how to make a small, precise functional change without restarting the full flow—that is the purpose of an Engineering Change Order (ECO).

Our flagship product, EasylogicECO, applies logic changes directly to the netlist at the current design stage and automatically generates a smaller, optimized patch of logic. This can reduce turnaround time from months to days and integrates seamlessly into existing design flows. It helps preserve timing closure while saving time and engineering resources. Use cases include pre-mask ECO, post-mask ECO (metal ECO), and product revisions or upgrades.

What application areas are your strongest?

Our strongest area is time-critical Functional ECO for digital chip design—situations where functionality must be changed late in the process, deadlines are tight, and manual fixes are difficult. Examples include correcting issues in complex digital designs such as CPUs, GPUs, DPUs, and SoCs after RTL freeze but before tape-out, and making RTL-driven changes to digital and mixed-signal chips after tape-out.

Many existing Functional ECO tools are add-ons to formal verification platforms rather than purpose-built ECO tools. Their capabilities can be constrained by the underlying verification technology, often resulting in long runtimes, limited automation,poor usability, and disappointing results.

Functional ECO is often needed at a critical moment, the tool must be easy to operate, require minimal setup, work out of the box, and deliver high-quality results quickly—ideally in a single run.

EasylogicECO was developed specifically for these needs. Its purpose-built flow and algorithms increase automation and improve both runtime and patch quality. Tests show it runs several times faster than traditional tools, while producing patches that are, on average, 30% better in quality; in some cases, the improvement exceeds 10×.This enables customers to resolve difficult chip-design issues quickly and efficiently.

What keeps your customers up at night?

As chip complexity grows and schedules tighten, design teams can no longer assume RTL will remain unchanged after freeze. First-pass tape-out success remains a major challenge, and a single logic bug found late can determine whether a product succeeds or fails. When an unexpected issue emerges, customers need to keep the project on schedule while minimizing risk and cost.

ECO work is unpredictable. Manual ECO requires expertise, is error-prone, hard to debug, may need multiple iterations, and is generally suitable only for simple changes. Some conventional tools are slow, difficult to use, or produce unexpected results. A failed ECO can delay a project or jeopardize the product.

Second, backend implementation must still converge. Even when an ECO is generated successfully, an oversized patch can make timing closure and physical implementation difficult. The process can also affect scan chains, low-power structures, or DFT constraints,

Finally, the ECO window is often extremely short—sometimes just before tape-out or even after mask release. Engineers may have little opportunity for repeated iterations, so speed, ease of use, and first-run quality are essential.

EasylogicECO is designed to address these challenges. Its proprietary, fully automated algorithms quickly generate smaller, optimized logic patches, with a streamlined user experience, short runtimes, and support for multiple design constraints—helping improve ECO success rates.

Competitive landscape and differentiation

Functional ECO is a highly specialized segment of the EDA market, with very few vendors offering automated solutions. In a market dominated by a small number of large vendors, we have established a differentiated position by focusing on logic-level changes late in the design process.

Our technology approach is different. Tools on the market mainly are built as add-ons to formal verification platforms and are constrained by the characteristics of those platforms. EasylogicECO is built around algorithms designed specifically for ECO, delivering improvements in performance and efficiency.

We also place strong emphasis on customer support. Although EasylogicECO can be integrated directly into an existing ASIC design flow, customers differ in their workflows and design practices. Simplifying tool usage and providing tailored engineering support are therefore important. We focus on two priorities: responding promptly to customer issues and delivering customized support as quickly as possible, so customers can complete ECO tasks with minimal delay and keep product development on schedule.

In short, Easy-Logic follows a distinct approach in the specialized Functional ECO market. For chip-design companies worldwide, we offer a focused, reliable alternative for late-stage logic changes—without dependence on a single EDA vendor.

What new features or technologies are you working on?

At the late stages of chip design, ECO tasks often arise under severe time pressure, while conventional methods may struggle to deliver results efficiently. Customers increasingly expect not just a tool that can perform an ECO, but one that can produce high-quality results quickly and predictably. We continue to advance both our products and our overall design-flow capabilities to meet increasingly complex needs.

We have introduced EasyAI ECO Suite, which integrates AI engines throughout the ECO workflow. Its first three intelligent engines are:

• Auto Partition intelligently divides very large circuits into solvable subproblems, reducing patch size by more than 20% on average and by as much as 90% in some cases.
  • Learning / I-Learning progressively searches for better structures across iterations, reducing patch size by more than 20% on average.
  • Smart Caching reuses results from previous runs and can reduce runtime by up to 80% in multi-iteration scenarios.

The solution has been validated in real projects at several leading chip-design companies. It is designed to address key limitations of conventional ECO approaches in patch size, runtime, and timing accuracy.

At the flow level, we are also expanding toward a comprehensive suite of incremental design tools. EasylogicECO currently supports Functional ECO, Scan Chain ECO, Low Power ECO, and Metal ECO. We are continuing to develop capabilities for Clock Tree ECO, Placement ECO, Timing ECO, and Routing ECO, with the goal of building an incremental design tool chain that covers the full range of late-stage chip changes.

How do customers normally engage with your company?

Customers typically work with Easy-Logic through software licensing. They first evaluate the tool in their own design environment to confirm that EasylogicECO meets their specific requirements. After a successful evaluation, the parties generally proceed with an annual license. Other flexible engagement models are also available and can be discussed based on each customer’s needs.

Companies with Functional ECO requirements are welcome to contact us:
Phone: 714-287-5154
Email: info@easylogiceda.com
Website: https://www.easylogiceda.com/en

Also Read:

Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026

Smarter ECOs: Inside Easy-Logic’s ASIC Optimization Engine

Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs