Easy-Logic, a leading provider of high-performance Engineering Change Order (ECO) solutions in Electronic Design Automation (EDA), will showcase its latest innovation — the EasyAI ECO Suite — at DAC in Los Angeles, July 27–29, 2026. This intelligent ECO solution integrates AI engines into the entire ECO workflow and systematically breaks through the traditional bottlenecks in patch size, runtime, and timing accuracy through its three core intelligent engines.
The suite covers the entire ECO flow from SYN ECO and DFT ECO to PR ECO, delivering AI-driven optimization at every stage. It addresses key pain points of traditional flows: uncontrollable patch sizes, redundant recomputation across iterations, and unpredictable outcomes.
Dr. Xing Wei, CEO of Easy-Logic, commented: “In the final ‘golden window’ of chip design, every ECO efficiency gain directly impacts time-to-market. EasyAI ECO Suite is not a single-feature upgrade, it is a systematic integration of AI across the entire ECO workflow, delivering smaller patches, faster iterations, and more accurate timing. We believe that as AI and EDA converge from concept to engineering practice, chip designers gain not just efficiency, but true controllability over their product schedules.”
Three Intelligent Engines, Redefining ECO
Auto Partition: Making Ultra-Large-Scale Complex Problems “Solvable”
When ECO deals with multimillion-gate changes, traditional tools get trapped in search space explosion. Auto Partition uses AI to analyze circuit node correlations and applies an “Analysis-Partitioning-Solve” loop to break complex problems into manageable sub-problems.
Benchmarks show Auto Partition reduces patch size by over 20% on average, and up to 90% in certain cases.
Learning/I-Learning: Iteratively Approaching the Optimal Patch
The intelligent learning engine combines proprietary Learning and I-Learning technologies to analyze structural and logic equivalences between old and new netlists, iteratively approaching the optimal structure. Even with netlists already optimized manually or by other tools, it continues to uncover further improvements.
Verified by multiple customers, patch size is reduced by over 20% on average, with some instances exceeding 50%.
Smart Caching: Accelerating Multiple ECO Rounds
Multiple ECO rounds are the norm in chip iteration. Smart Caching builds a “Store-Reuse-Iterate” cycle: the first run deep-learns the circuit structure and ECO changes, saving the entire process as experience; subsequent runs directly reuse past results, eliminating redundant computation.
Benchmarks show that, without any parameter changes, runtime is reduced by up to 80% or more in multi-iteration scenarios.
The three intelligent engines work in synergy across the entire ECO workflow. Our team will be at DAC 2026 to demonstrate how EasyAI ECO Suite integrates into existing design flows, with live product demos and in-depth discussions on tailored solutions for diverse applications.
We sincerely invite industry peers to visit our booth #958.
Also Read:
Smarter ECOs: Inside Easy-Logic’s ASIC Optimization Engine
Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs
WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
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