With increasing density and functionality of chips at extremely thin silicon and metal layers, temperature has become critical. The temperature situation can become worse with wireless enabled 24/7 power-on devices. In such a scenario, a device must manage its thermal profile dynamically to keep the temperature within tolerable limits. Of course all precautions must be taken to budget for voltage, power and temperature while designing an SoC. It’s prudent to also have mechanisms embedded within the SoC so that it can self adjust its operations when temperature hotspots arise. What are such mechanisms? Thanks to the innovative IP world; it provides IP that can continuously monitor voltage and temperature, detect temperature hotspots and guide the chip to adjust temperature in the hotspot regions.
This Monday, it was a pleasant occasion to watch an on-line videoat Cadencewebsite where Bob Salem, Product Marketing Director at Cadence explained how such an IP works and can be used in chips to optimize their performance, increase reliability and lengthen battery life. This is actually an explanation on whiteboard, recorded and posted on the Cadence website on a Wednesday. Cadence popularly calls these videos as ‘Wednesday whiteboard videos’! Let’s see what is there to learn in it.
Looking at the thermal imaging of a die, maximum temperature can be seen at a hotspot. The temperature degrades as we move farther from the hotspot in all directions. In the above picture, a hotspot is shown at 125[SUP]o[/SUP]C and the outermost circle periphery is at 40[SUP]o[/SUP]C. The first problem at hand is to locate the hotspots on the die and then take appropriate steps to cool down those areas.
On the left side in the above picture is a simple conceptual circuit diagram of the circuitry that goes into the voltage / temperature monitoring IP. A multiplexor takes multiple inputs from sensors for temperature, voltage, and percentage of moisture in a particular area where the IP is located and outputs the desired information in analog form. The analog data is then converted into digital form by an ADC (analog to digital converter). The digital data goes into a processor which deciphers the information and takes appropriate action. Depending upon the severity of temperature, either it can turn-off the power or lower the frequency of operation in that region.
As shown in the thermal profile diagram, the IP blocks can be spread across the die to record and process the voltages and temperatures in different regions. A good IP and well designed topology of an SoC and IP placement regions within it can be very effective for the SoC to manage its temperature profile to be within prescribed limits at all times. Clearly, this enhances the life and long term reliability of a device containing SoC with such IP. It also improves performance of the device, the device handling and its battery life.
It’s an interesting video where Bob Salem explains the story in very simple terms. There is no registration required for this video and it takes less than five minutes.
After watching the video, I tried to explore what kind of IP portfolio Cadence has for voltage and temperature monitoring. It does have a good range of power / sensor IP consisting of power low drop-out (LDO) voltage regulators, temperature sensors, and application specific analog designs, and so on. Look at the page at Cadence website here.Share this post via: