Tanner EDA at DAC

Tanner EDA at DAC
by Daniel Payne on 06-14-2011 at 2:40 pm

Intro
For 22 years now Tanner EDAhas been in the business pf offering tools for AMS and MEMS designers. I learned what’s new at DAC on Tuesday morning.

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Notes
Nicholas Williams – Director of Product Management

Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
W-Edit – is the waveform… Read More


Blue Pearl at DAC

Blue Pearl at DAC
by Daniel Payne on 06-14-2011 at 1:03 pm

Intro
It’s all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what’s new for 2011.

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Notes

What’s New in 2011 at Blue Pearl Software

New designer experience, ease of use. Brand new GUI.

Work with RTL to synthesis tools to Read More


Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 2 of 2)
by Daniel Payne on 06-14-2011 at 12:43 pm

Dipesh Patel, VP Engineering, ARM Physical IP

Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?

Standard Cells: multi-channel, multi-vt (4) libraries

Memory Compilers:Read More


Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)
by Daniel Payne on 06-14-2011 at 12:26 pm

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.
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Notes
Why 32/28nm
Lower power, high integration requirements, mobile applications

What is Ready?
IP is qualified (ARM, Memories, Foundation IP, SNPSRead More


A Birds-Eye Overview of DRC+

A Birds-Eye Overview of DRC+
by Daniel Nenni on 06-13-2011 at 10:57 pm

The GlobalFoundries DRC+ platform is one of the most innovative DFM technologies and was well represented at #48DAC. In case you missed it, here is a reprint of a DRC+ overview from GFI just prior to #48DAC:

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DRC (Design Rule Constraints) are the fundamental principles in constraining VLSI (Very Large Scale Integration)… Read More


CyberEDA adds a Transistor-Level Debugger

CyberEDA adds a Transistor-Level Debugger
by Daniel Payne on 06-13-2011 at 6:34 pm

Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.

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Notes

2010 – Announced a debugger

2011 ADDS Debugger – trace at the transistor level your design
– … Read More


QuickCap for IC Extraction at DAC 2011

QuickCap for IC Extraction at DAC 2011
by Daniel Payne on 06-13-2011 at 6:08 pm

Intro
John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.
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Notes
John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)

John Schritz
– Digital Signoff, extraction
– QCP: 2.5D RC for full ASIC designs
– QuickCAP NX: 3D field solver
– QCP:… Read More


HSPICE gets Faster, better Convergence

HSPICE gets Faster, better Convergence
by Daniel Payne on 06-13-2011 at 5:53 pm

Hany El Hak – Product Marketing Manager

Frederik Iverson – AE
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Scott Wetch – HSPICE Architect

HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.

Synopsys AMS Portfolio – wide range of tools
– Custom Designer: IC schematic and layout… Read More


Physical IP Group at ARM

Physical IP Group at ARM
by Daniel Payne on 06-13-2011 at 5:45 pm

After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division

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Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).
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Q: Do you favor any EDA tools for creating your IP?
A: No, … Read More


iPDKs and Analog Constraints

iPDKs and Analog Constraints
by Daniel Payne on 06-13-2011 at 5:09 pm

Lunch time Monday at DAC and I learned about what’s new at the IPL Alliance in 2011.
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IPL Sponsors: Magma, Mentor Graphics, Springsoft, Accelicon, Ciranova, Synopsys, TSMC, TowerJazz, Jedat, Tanner EDA

Two major projects:
1) iPDKS
2) Analog Constraints… Read More