How early symmetry validation eliminates costly late-stage respinsBy Mauli Shah, Product Engineer, Siemens Analog and…Read More
Rethinking Formal Verification in the AI EraBy Kanav Arora, ML Researcher at ChipAgents Most…Read More
CEO Interview with Ann Wu and Akash Levy of SilimateAnn Wu is Co-founder & CEO of Silimate.…Read More
From Process Learning to Production Control: Characterization for the Era of Heterogeneous SystemsEvery generation of semiconductor innovation has relied on…Read More
Five Myths about the Current Memory BoomThe current semiconductor memory boom is mainly an…Read More
Over the years DRC tools have done an admirable job of keeping pace with the huge growth of IC design size. Yet, DRC runs for sign off on the full design using foundry rule decks take many hours to complete. These long run times are acceptable for final sign off, but there are many situations where DRC results are needed quickly when small… Read More
-A repeat of the auto industry bailout of self inflicted issues?
-Not just money but systemic change is needed
-Perhaps chips need an Elon led revolution like autos & space
-Govt $ need focus not thrown into existing spend avalanche.
Are chips a replay of the auto industry bailout a decade ago? Deja Vu all over again.
The… Read More
Dan is joined by Krishna Settaluri, Co founder and CEO of Blue Cheetah. Krishna received his Ph.D. in electrical engineering from UC Berkeley and masters and bachelors from MIT specializing in design automation of high-speed silicon photonic links using analog generator technology. Krishna has worked at Apple, Google, Caltech… Read More
Prakash Murthy is the co-founder & CEO of Atonarp, a leading molecular diagnostics company HQ in Tokyo Japan. Murthy has two decades of experience in engineering management and entrepreneurial ventures. Murthy also co-founded Inspiration Technologies and C2Silicon Software and served as the CEO of Core Solutions Inc.… Read More
For IC designs there are many data formats used throughout the logical and physical design process, and one of those file formats is called LEF, an acronym for Library Exchange Format, created by Tangent, an early EDA company with Place and Route tools that was acquired by Cadence way back in March 1989. LEF generation times can become… Read More
In today’s System-on-Chip (SOC), analog blocks are used in many places such as I/O cells for communication, PLLs for generating clocks, LDO’s for converting supply voltage to internal rail voltage, Sensors for qualifying external characteristics such as temperature, light, motion, etc. However new advanced designs now require… Read More
In the early years of Cadence their growth was bolstered through many well-timed acquisitions, however over the last several years I’ve noticed a distinctively different trend where they have internally developed EDA tools. I had a Zoom call with Jay Madiraju from Cadence, who markets their newly announced Fast SPICE … Read More
This standard has been around in one form or another for over ten years and was then arguably ahead of its time. RTL designers were confused: ‘We already have RTL. Why do we need something else?’ I also didn’t get it. Still, the standard plugged ahead among the faithful and found traction among IP vendors. Particularly as a common format… Read More
The TSMC Symposium kicked of today. I will share my general thoughts while Tom Dillinger will do deep dives on the technology side. The event started with a keynote by TSMC CEO CC Wei followed by technology presentations by the TSMC executive staff.
C.C. Wei introduced a new sound bite this year that really resonated with me and that… Read More
The continued innovation and widespread adoption of connected devices — the internet of things (IoT) — has resulted in a vast range of conveniences that improve our lives every day. At the same time, the ubiquity of IoT devices, which market watchers estimate to be in the tens of billions, also makes it more attractive to bad actors… Read More
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ASML High-NA EUV is Not Ready for High-Volume Production