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Semiconductor Expert Forum

Podcast EP18: The Story Behind Combining Methodics and Perforce

Podcast EP18: The Story Behind Combining Methodics and Perforce
by Daniel Nenni on 04-30-2021 at 10:00 am
Categories: EDA, Perforce

Dan and Mike are joined by Simon Butler, founder of Methodics and Brad Hart, CTO of Perforce. We explore the acquisition of Methodics by Perforce, including motivation, strategy and a look to the future. We also discuss some of the history of Methodics and how they became successful.

For further discussion, visit their blog The… Read More

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CEO Interview: Rich Weber of Semifore, Inc.

CEO Interview: Rich Weber of Semifore, Inc.
by Daniel Nenni on 04-30-2021 at 6:00 am
Categories: CEO Interviews, EDA, Semifore

Rich Weber

Rich Weber co-founded Semifore in 2006 with Jamsheed Agahi. Rich has a long history of complex chip and system design at companies including Data General, Stardent, Silicon Graphics, StratumOne and Cisco Systems. He received an MS in Electrical Engineering and a BS in Computer Engineering from the University of Illinois, Urbana-Champaign.… Read More

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Lam Research performing like a Lion – Chip equip on steroids

Lam Research performing like a Lion – Chip equip on steroids
by Robert Maire on 04-29-2021 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services

NASDAQ LRCX LAM

– Business is about as good as it gets- $75B WFE in 2021?
– China remains strong at 32% despite SMIC lack of license
– NAND remains 48% of revs versus 31% foundry
– DRAM steady @ 14% – Service was record $1.3B

Strong results in a strong market

Lam reported revenues of $3.85B and EPS of $7.49 for the March… Read More

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Accelerating Cache Coherence Verification

Accelerating Cache Coherence Verification
by Bernard Murphy on 04-29-2021 at 6:00 am
Categories: EDA, Synopsys

Cache coherence checking min

It would be nice if there were a pre-packaged set of assertions which could formally check all aspects of cache coherence in an SoC. In fact, formal checks do a very nice job for the control aspects of a coherent network. But that covers only one part of the cache coherence verification task. Dataflow checks are just as important, where… Read More

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Chip Shortage, COVID-19 Unmasks Transit Gaps

Chip Shortage, COVID-19 Unmasks Transit Gaps
by Roger C. Lanctot on 04-28-2021 at 10:00 am
Categories: Automotive

Chip Shortage COVID 19 Unmasks Transit Gaps

I haven’t traveled a lot during the COVID-19 pandemic, but I have flown a few times around the U.S. As a former frequent flyer I pride myself on anticipating most travel circumstances and not being surprised or blindsided, but two recent visits to Austin, Texas, changed that when I couldn’t find a rental car.

It was just 12 months … Read More

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Arteris IP Contributes to Major MPSoC Text

Arteris IP Contributes to Major MPSoC Text
by Bernard Murphy on 04-28-2021 at 6:00 am
Categories: AI, Arteris, Automotive, IP

Wileybook min

You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor… Read More

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ASML early signs of an order Tsunami – Managing the ramp

ASML early signs of an order Tsunami – Managing the ramp
by Robert Maire on 04-27-2021 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services

ASML Stock Price 2021

Taiwan and Korea represented 43% and 44% respectively with China at 15% and Japan and the US in the far distance.

ASML a tidal wave of orders

On the call management talked about logic potentially being up 30% in 2021 and memory being up potentially 50%. While we thing foundry/logic will clearly be on fir we think memory will lag a bit.… Read More

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Agile and Verification, Validation. Innovation in Verification

Agile and Verification, Validation. Innovation in Verification
by Bernard Murphy on 04-27-2021 at 6:00 am
Categories: Cadence, EDA

Innovation image 2021

Agile methods in hardware design are becoming topical again. What does this mean for verification? Paul Cunningham (GM, Verification at Cadence) and I continue our series on research ideas. We’re also honored this month to welcome Raúl Camposano to our blog as a very distinguished replacement for Jim Hogan. As always, feedback… Read More

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Small EDA Company with Something New: SoC Compiler

Small EDA Company with Something New: SoC Compiler
by Daniel Payne on 04-26-2021 at 10:00 am
Categories: Defacto Technologies, EDA

Defacto SoC Compiler

I read the semiconductor press, LinkedIn and social media (Twitter, Facebook) every morning along with an RSS feed that I setup, staying current on everything related to using EDA tools to make the task of SoC design a bit easier for design teams. A recent press release announced a tool called SoC Compiler, so my curiosity was piqued… Read More

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PCIe 6.0 Doubles Speed with New Modulation Technique

PCIe 6.0 Doubles Speed with New Modulation Technique
by Tom Simon on 04-26-2021 at 6:00 am
Categories: IP, Synopsys

PCIe 6.0 Eye

PCI-SIG has held to doubling PCIe’s data rate with each revision of the specification. The consortium of 800 companies, with its board consisting of Agilent, AMD, Dell, HP, Intel, Synopsys, NVIDIA, and Qualcomm, is continuing this trend with the PCIe 6.0 specification which calls for a transfer rate of 64 GT/s. PCI-SIG released… Read More