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Altera’s New Dual ARM® Cortex™-A9 SoC Arria® and Cyclone® V FPGA Families

Altera’s New Dual ARM® Cortex™-A9 SoC Arria® and Cyclone® V FPGA Families
by Daniel Nenni on 01-03-2012 at 7:29 pm

Altera recently introduced versions of their new Arria® and Cyclone® V FPGA families that incorporates a dual ARM®Cortex™-A9 MPCore hard core. These parts are particularly interesting to NARD as it’s consistent with the NARD concept of offering platforms unified by a common ARM® host core and a variety of controller/coprocessor cores. Here is a block diagram of the ARM MPCore:

(Click to enlarge diagrams)

One can see that it contains many of the I/O peripherals one has come to expect from an ARM processor. Two items are of interest to NARD:

  • CAN 2.0 – this automotive oriented control bus is extending its reach beyond its automotive industry origins. Originally developed by Robert Bosch GmBH, It is becoming popular in the industrial area as a control fieldbus.
  • Ethernet with IEEE 1588 PTP support – precise time distribution is to be supported by all NARD platforms. It is becoming accepted in the industrial and communications market place. It is being extensively used in Mobile backhaul applications and Electric Utility Smart Grid applications.

The Coresight Embedded trace and JTAG support has been extended into the FPGA space. The SoC FPGA also supports a variety of power up initialization modes and boot modes.

One feature that caught my eye was the L2 cache coherency scheme. Here is a diagram of the scheme:

We see that the L1 and L2 caches are both kept in sync with the other using a bidirectional coherency mechanism. However, FPGA accessess to the Shared ARM SDRAM memory space only implements a unidirectional coherency scheme. I guess the FPGA only needs to be aware of L2 getting dirty and needs to refresh its copy. The L2 cache will know its cache is dirty from the bus snooping logic, I guess. More investigation on my part is necessary to fully understand how coherency is assured.

These parts invite a direct comparison to the Xilinx ZYNQ™-7000 family of Extensible Processing Platforms (EPP). Xilinx took their new midrange Kintex™-7 FPGA and incorporated a hard ARM® Cortex™-A9 dual MPCore.

In response to the ZYNQ™-7000, Altera has provided a low cost, entry level SoC in their Cyclone® V FPGA and their mid range Arria® V FPGA.

When examining the MPCore implementation and their interconnects, I was struck by how similar they were. In hindsight, that should not have been a surprise, as both vendors are using TSMC’s 28nm process, so they probably started at identical points.

Here is a block diagram of the Altera SoC architecture:

It’s interesting to compare and contrast what hard IP features Xilinx and Altera are incorporating into their parts. Both companies have incorporated hard IP PCIe Gen 2 cores into their SoC. Xilinx supports a single x8 or x4 depending on the model (x1, x2, x4?) and Altera supports up to 2 Gen 1 and Gen 2 x1, x2 and x4 and Gen 1 x8. Both parts also support SHA and AES encoding.

Altera is incorporating up to three additional multi-port SDRAM controllers. Xilinx is incorporating a multi channel, 1Msps 12 bit Analog-to-Digital converter system.

NARD is particularly attracted to the additional hard SDRAM controllers. Memory is one thing that constrains many of the GPU devices in numerical applications. The hard controllers will not take resources away from coprocessor implementations. NARD will explore the use of these additional memory controllers in compute intensive applications. Altera’s recent announcement for its OpenCL initiative for FPGAs is an important component towards making the SoC a cost and power efficient compute platform.

One area where Altera appears to have a distinct advantage is in the serial transceivers. The Cyclone line supports 3 and 5 Gbps transceivers and the Arria line supports 6 and 10 Gbps, supporting two distinct price and performance points. Xilinx supports 6 and 10 Gbps. The Altera FPGA appears to have additional hard IP support for:

  • 3G and 6G Basic – 0.600 to ~6.375
  • Gigabit Ethernet – GbE 1.25 Gbps
  • XAUI – 3.125 Gbps
  • Serial Rapid I/O – SRIO 1.25 to 6.25 Gbps
  • SDI – 0.27, 1.485, 2.97 Gbps
  • SATA – 1.5, 3.0, 6.0 Gbps
  • CPRI – Common Public Radio Interface – 0.6144 to 6.144 Gbps
  • GPON – ITU-T G.984 Passive Optical Network – 1.25 and 2.5 Gbps

Of particular interest to NARD is the SRIO and SATA IP. SATA would be an important component to build a stand-alone, general-purpose computer platform. SRIO interconnects is something NARD will focus on.

The one problem is availability. The Xilinx part is now shipping in limited quantities. The Altera parts won’t be available till mid year. This time frame should work for NARD, as we will initially focus on the closed loop controller platforms based on TI’s Hercules and Concerto processors. Second in line is a general purpose, mainstream platform based on the TI AM335x. Third up will the SoC FPGA platform or the multi-media focused platform based on the TI Sitara AM387x or DaVinci DM414x processors.

It will be a real challenge to get the DDR3 1066MHz SDRAM interface running along with the SATA and PCIe Gen 2. Getting a working design under NARD’s belt in a reasonable time frame will ultimately determine the future viability of NARD LLC in the embedded marketplace.


–Jim Nakama

NARD LLC

Additional Resources
Altera Arria V
Altera Cyclone V


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