Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done

Buying IP is just a little bit more complicated than buying a pair of shoes. A lot of IP is configurable and requires attention to various design and configuration parameters. We live in an age where commercial soft IP is used pretty often in designs, so people have developed increasing comfort in the process that is required to achieve integration. Hard IP definitely takes it up a level – there are more process specific details that require attention. Nevertheless, it seems that commercial hard IP has become viable and is being used frequently as well. So, the industry is making both hard and soft commercial IP work. But there is a new twist in the IP market, embeddable field programmable gate arrays, or eFPGA as Achronix likes to call their offering.

There are huge and easily grasped advantages to embedding FPGA fabrics inside of SOC’s. Off chip communication is costly from a power, BOM and throughput perspective. Bringing a system’s FPGA onto the SOC is a big win, and though it requires some extra thought, it seems the business and technical model that Achronix uses to onboard customers is well thought out and highly effective. Achronix has put together a white paper explaining the process for evaluating and implementing their embeddable FPGA fabric for use in SOC’s.

In many ways, embedding an FPGA fabric is a lot like embedding a processor, so the evaluation has to look at the target RTL for the FPGA and the resources it will optimally utilize. The elegant part of this is, of course, that the FPGA core can be precisely configured to meet the power, performance and area requirements of the final system. The Achronix white paper goes through this step by step. The first step is a technical discussion with the customer regarding requirements. This is usually done after an NDA so the appropriate level of technical detail can be covered.

The customer can also download the ACE design tools that are optimized for the Achronix eFPGA target. It includes an Achronix-optimized version of Synopsys Synplify Pro that fully supports Achronix Speedcore. The ACE toolkit can provide area, power timing and resource utilization information. It also supports debug and static timing analysis for both functional and timing-annotated simulation.

Achronix supplies two preconfigured Speedcore eFPGA instances for use as targets to help customers understand utilization and optimization. Customers can take their RTL and synthesize it with the ACE toolkit and then evaluate the results to determine what the optimal configuration would be for their customized instance. Of course, there will probably be some changes required to adapt from an existing discrete FPGA architecture to the Speedcore eFPGA. Achronix offers LRAM in addition to BRAM. This LRAM comes as a 4,096 bit configuration that is 128 x 32 and is suitable for buffering tasks. Another difference is that Speedcore uses a 4 input LUT, rather than the more common 6 input LUT in other architectures. Achronix has found that empirical data shows this is more efficient for a majority of programmable logic applications.

There is more information in their white paper about how Achronix works with their customers to evaluate the use of embeddable Speedcore eFPGA in their designs. Because Achronix has enjoyed increasing success with their discrete Speedster 22i FPGA, the evaluation and development steps are well understood, and they have ample experience to make the entire process go smoothly. Achronix also seems to place proper significance on technical dialog with their customers to ensure silicon and design success. The full white paper is available for reading on their website. It’s good to see, despite the additional complexity, that SOC designers who want to take advantage of the benefits of embedded FPGA fabric can fully understand the considerations and benefits before committing.