IO Design Optimization Flow for Reliability in 28nm

User group meetings are a rich source of information for IC designers because they have actual designers talking about how they used EDA tools in their methodology to achieve a goal. Engineers at STMicroelectronicspresented at a MunEDAUser Group on the topic: I/O Design Optimization Flow For Reliability In Advanced CMOS Nodes. That presentation was then turned into a paperat the IRPS 2014 (International Reliability Physics Symposium) held in Hawaii just two months ago. I’ll provide my take on this 5 page paper in this blog. Reliability is pertinent to me because I’ve had two consumer devices fail in the past year – an iPad 3 and MacBook Pro. Maybe both devices would still be working if Apple did more reliability simulations on the components in their iPad and if memory makers did more reliability simulations on their DRAM chips.

There are three main wear-out mechanisms categorized by reliability engineers:

• BTI – Bias Temperature Instability, where the Vt degrades over time.
• HCI – Hot Carrier Injection, where an electron or hole gets enough energy to break an interface state, becoming trapped in the gate dielectric, changing switching.
• TDDB – Time Dependent Dielectric Breakdown, where the silicon dioxide in the CMOS gate breaks down creating a conducting path through the oxide to the substrate.

The promise of the MunEDA flow for STMicroelectronics is to automatically analyze and size devices that meet reliability requirements on I/O circuits on a 28nm CMOS process.

Reliability modeling needs to occur across the entire Vgs and Vds design space. In STMicroelectronics’ FDSOI PDK, MunEDA uses Eldo UDRM simulation results, including BTI, HCI and TDDB effects.

A high age rate is shown in Red, while a low age rate is depicted with the Blue color. Age rate means the rate of defect nucleation that causes device degradation, like: gate leakage, oxide breakdown, or hard breakdown. Equations were shown for the Mean Time To Failure (TTF), failure rate (FR) and Failure in Time (FIT).

The EDA tool flow for reliability simulation uses a SPICE circuit simulator (ELDO in this case for STMicroelectronics), along with aging model parameters, a user-defined reliability model, and a comparison of aged simulation versus fresh simulation.

Designers generate an aging report with useful information like: Vth shift, mobility degradation and FIT numbers. Moving from theory into actual practice, an I/O buffer circuit was selected for analysis and automated sizing using both a 28nm bulk and UTBB FDSOI process.

The tool flow for automated transistor sizing including aging and reliability constraints uses the WiCkeD tool from MunEDA:

What makes this flow different is that MOS widths and lengths are changed not only within Reliability Design Rules (RDR), but also taking into account reliability SPICE simulations during the optimization, thus keeping the growth in layout area to a minimum. There are multiple circuit simulations performed to determine the stress per device, and then aged performances are simulated to create reliability constraints for sizing.

Restricted design parameter space Pi to fulfill all the performances f(p) under reliable constraints c(p)

Once optimization is complete, the designers could choose a trade off between different sizing strategies for: Area, Performance, Reliability.

Silicon Results

A 28mm test chip was built to validate and compare actual results versus predicted results. A ring oscillator circuit was used for dynamic stress with maximum operating frequencies by connecting five bidirectional I/O cells together.

The frequency of the ring oscillator was simulated and compared versus silicon as a function of the stress time, showing close correlation:

Another comparison of reliability simulations shows good accuracy of the WiCkeD tools versus silicon:

Summary

You can now use a tool flow that optimizes MOS device sizes taking into account reliability factors. The WiCkeD tools from MunEDA were shown to predict aging and reliability effects that matched silicon. The steps used in this flow look easy enough to learn, and result in a more robust circuit that meets your reliability requirements. The complete five page paper can be read online.