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Cadence Grows VIP Business – What’s New?

Cadence Grows VIP Business – What’s New?
by Pawan Fangaria on 10-04-2013 at 10:00 am

VIPs (Verification IPs) are really important in this complex world of SoCs which involve various IPs, interfaces and continuously evolving protocols and standards, thus making the task of verifying an overall system extremely challenging. And the verification must be done in minimum possible run-time and memory consumption. Add to it, the tremendous pressure of time-to-market. In such a situation, this concept of VIP is a boon to the semiconductor design industry. A VIP is like a plug-and-play verification component (configurable under different environments) which enables any design to be tested, quickly and easily, at block, sub-system or SoC level.

Too many standards and protocols for buses, interfaces and MIPI (Mobile Industry Processor Interface), continuously evolving into newer versions with improved capabilities (such as speed, bandwidth, encoding, decoding etc.) has frequently demanded newer VIPs. Small capital investment and large demand in this business led to the emergence of numerous players. VIP business turned into a commodity business, albeit important and essential. Naturally, there was a consolidation move some time ago and closest business adjacencies, EDA giants acquired a few of the VIP companies; notably Cadenceacquired Denali and Synopsysacquired nSys and ExpertIO.

Why is it important? It complements the SoC platform solution to large extent by easing the burgeoning verification task. Again, by conforming to certain standards, it becomes generally available to semiconductor design and consumer electronics industry. Naturally the strategy which plays a big role in this is how fast one can bring up a new VIP conforming to a new set of standards and grab the market share.

This particular business caught my attention when, about a month ago, I heard Cadence announcing semiconductor industry’s first VIP for HDMI 2.0 (High Definition Multimedia Interface), which conforms to major verification languages, logic simulators and verification methodologies including UVM (Universal Verification Methodology). I am sure, Cadence will gain significant market share in this with companies like STMicroelectronicsand Sony already using it.

The HDMI 2.0 VIP announcement prompted me to look further into what exactly is being offered. And I came across a whitepaper, jointly written by ST and Cadence, which provides great level of detail about the much improved HDMI 2.0 (earlier, or rather current version is HDMI 1.4a/b) and the challenges involved in making of that VIP. I am not going into all that detail here, but it’s worth mentioning some of the design and verification challenges which appeared due to HDMI 2.0 as compared to HDMI 1.4a/b, and how the VIP caters to those.


[Block diagram – HDMI transmitter (Source) and receiver (Sink) device]

Among design challenges are – i) Re-designing the video encoder to be synthesized at 600MHz (as compared to 300MHz with 1.4b), ii) Re-designing of several other blocks to accommodate new timing constraints and misalignment of control logic between video data and video sink, iii) Addition of a new state “scrambling_enb” in the state machine to support scrambling for EMI (Electromagnetic Interference) / RFI (Radio Frequency Interference) reduction at TMDS (Transition Minimized Differential Signalling) bit rate of lesser than or greater than 3.4Gb/s, iv) Scrambling using LFSR (Linear Feedback Shift Register) and validating the data decoded by the sink VIP, with increased complexity at 600MHz. There are many other challenges mentioned in the whitepaper.

Verification challenges have increased exponentially in HDMI 2.0 due to huge video frames, multiple streams, complex data structures with multiple layers, and scrambling, encoding and encryption of the digital data at high frequency. All supported video formats with all the possible configuration settings, such as frame rate, pixel encoding, color depth etc. and all audio formats with appropriate configurations (channel allocation, audio frequency etc.) must be verified.


[VIP configured as HDMI source for sink DUT]

A VIP to be able to thoroughly verify a DUT (Design Under Test) under such complex protocols must be robust and flexible enough to accommodate varied configurations. HDMI VIP includes static and dynamic configuration parameters, customizable frame formats, on-the-fly data-integrity and signal-integrity checks, frame boundary detection, user controllable options etc. that provide 100% coverage.

A layered and scalable architecture of HDMI VIP provides a smooth and timely migration from IP-level verification environment to SoC-level verification environment. Click on the whitepaper to know more details. It’s an interesting read!!

lang: en_US


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