Webinar: Signoff for Thermal, Reliability and More in Advanced FinFET designs

In automotive applications, advanced FinFET processes are great for high levels of integration and low power. But they also present some new challenges in reliability signoff. Ansys will be hosting a webinar to highlight the challenges faced by engineers trying to ensure thermal, electromigration (EM) and electrostatic discharge (ESD) robustness in advanced SoCs and to show how ANSYS tools and flows can help meet these goals.

REGISTER HERE for the Webinar September 27[SUP]th[/SUP] at 8am PDT

This is of more than passing importance in automotive applications. Cars and other vehicles are expected to have 15+ year lifetimes, far longer than the consumer electronics we normally think of as benchmarks. These systems are also held to much higher expectations, often in much more challenging environments, for thermal problems, electromigration and ESD. And these problems are only going to get worse as autonomy support increases in our cars and safety functions are expected to be 100% dependable through at least the warranty period.

Reliability is also a big concern in mobile and high-performance computing, though in different ways. The average lifetime of mobile devices is likely to grow quite significantly, party because the thrill of constantly updating our phones/pads/watches is wearing off and partly because there is no such thrill in industrial applications. Businesses will be motivated to look for more reliable alternatives if scanning and other devices start to go bad after 2 years.

In high-performance computing, thermal and reliability are both significant cost concerns, directly affecting to the costs of cooling in data centers and repair/replacement and downtime which can directly affect committed throughput for cloud providers.

Demonstrating the level of importance of this area, TSMC and ANSYS recently announced a new Automotive Reliability Solution Guide. ANSYS and TSMC collaborated on this first-of-its-kind guide, incorporating various reliability capabilities in one place to support customers’ IP, chip and package development for automotive applications in TSMC’s 16-nanometer FinFET Compact Technology (16FFC) process and Automotive Design Enablement Platform (ADEP).

Join ANSYS to learn how ANSYS solutions offer comprehensive chip-package-system thermal analysis, as well as thermal aware EM sign-off, for finFET designs. Discover how ANSYS PathFinder can help ensure ESD integrity from the IO/IP level to the SoC for human body model (HBM) and charged device model (CDM) analysis. This session will also cover best practices for ESD model hand-off from IP to SoC for chip ESD validation, and generating SoC-level ESD models for system-level ESD simulations.

REGISTER HERE

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