As Moore’s law started saturating on a single semiconductor die, the semiconductor community came up with the approach of growing vertically by stacking dies one above other in a 3D-IC arrangement. However, a major concern with a 3D-IC is that the heat generated by each die can get trapped in the stack, and hence it’s extremely important to accurately model the thermal map of Chip-Package-System (CPS) as a whole in order to manage the heat in a 3D-IC. Accurate thermal profiling is necessary for right placement of thermal sensors, T[SUB]max[/SUB] control and thermal-aware EM sign-off. The thermal responses are coupled with power map (especially at 28nm and below) due to leakage current in device layers and self-heating of interconnect wires. Considering the practical situations, a dynamic thermal analysis along with accounting of time factor due to thermal capacitance of the package and system can provide a realistic approach to thermal analysis in 3D-ICs.
Researchers at Apachestudied the effect of heat capacitance to the temperature rise on a chip in BGA package as shown above. In the power up transient analysis, it is observed that in the chip-package (CPS) mode, the steady state is achieved in more than 100 seconds, while in chip-only mode (i.e. ignoring heat capacitance in the materials outside the die) the same is achieved in just about 0.6 seconds, thus leading the temperature to respond quickly to power changes in chip-only mode.
A step-by-step solution approach applied on finite element (FE) model of the complex 3D-IC structure which can be quite large and can invite the solution steps thousands of times in the full thermal transient analysis, is impractical. A simple procedure to obtain temperature transient response for any location in the FE model is by using Green’s function of temperature from the step change of power on a chip. A graph of temperature response on a hot spot on chip using full thermal transient and Green’s function approach for a 40-sec power on and off in the same CPS environment shows that the results are almost similar whereas Green’s function approach is at least 60x faster. In case of larger FE models with more degrees of freedom, the difference in simulation time can be still more significant.
Apache’s chip power tools (RedHawk and Totem) can be used to compute the average power based on event-driven (if VCD file is available), vectorless (if no VCD file is available) or mixed-mode (if partial VCD file is available) approach. Chip power depends on usage which, for example for a smartphone, can be different for voice, email or streaming. In order to control power, a chip can be made to operate in different modes. A temperature sensor can be handy in sensing when the limit crosses in high-performance power mode and initiating the chip into low-performance low-power mode until the temperature drops to a desired level.
The power tools are used to generate a temperature-dependent power library called Chip Thermal Model (CTM). Using CTM, a chip thermal tool, Sentinel-TI(Thermal and mechanical Integrity) is sufficient to generate converged thermal and power results. CTMs can be hierarchical, assigned to multiple sub-regions such as blocks or clusters in an SoC and adapted to configurable stack of dies in a 3D-IC.
Stephen H. Pan, Norman Chang and Tadaaki Hitomi at Apache in their technical paperat IEEE 3DIC 2013 conference, presented testcases using the CTM and Green’s function approach to predict thermal transients at locations in a wire-bond BGA and in a 3D-IC design with flip chips.
Transients in a BGA package with 16x16mm substrate, 240 solder joints, wire-bond die of 5×5.1mm, Theta_JA range from 76 to 81 C/W and mounted on a 100x100mm 4L thermal board were calculated at several locations under different power modes. A series of power activities were applied to check the consistency of thermal wave with power activation. The temperature level for each location is affected by both the hot spot location and the overall average power level.
Above images show chip power generated with three different power modes, i.e. a CTM for each of these conditions and temperature profiles on-chip and in package along with their corresponding power map for condition #1.
Transients in a 3D-IC package (12x12mm, 6L, and 144 solder joints); with an SoC (5.2×5.2mm) at the bottom and a MEM (1.9×1.9mm) and LOGIC (2.72×2.72mm) at the top were calculated using hierarchical CTMs which are also configurable. The CTM for the whole SoC is not available because the IPs in some of the blocks do not have power map available, except the total power consumption of each block. However, part of the power on the SoC is in a cluster and its CTM can be generated. There are high and low power modes in this 3D-IC design to which the device switches according to existing temperature.
Above images show the temperature dependence of total power in the cluster and its distribution at converged temperature, and temperature profile in the 3D-IC chips at the high power mode. Thermal responses at different power modes were studied.
This methodology for 3D-IC dynamic thermal analysis is useful in the back-annotation to the individual die for accurate thermal sensor placement, T[SUB]max[/SUB] control, and thermal-aware EM sign-off. The methodology is described in more detail with several references in the actual paper. It’s an interesting read.
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