Most IC engineers learn best by hands-on experience when another more experienced person can show us what to do. If you cannot find that experienced person, then the next best thing is a video from an expert. I was surprised to find out that video was so important today that the #2 most viewed web site on the Internet was www.youtube.com, just behind #1 www.google.com. At SemiWiki we also believe that videos can help you to learn quicker, especially when it comes to using the popular Calibre DRC and LVStools from Mentor Graphics. We’ve setup a Wiki page of videos and here’s an overview of what you’ll learn in this series of six videos.
James Paris shows us how to invoke Calibre from within the Synopsys IC Compiler tool by using a GUI. Instead of running separate DRC tools at each stage (Floorplan, Power and Ground, Placement, Clock Tree Synthesis, Final Route), why not use the sign-off DRC tool within each stage. An interactive DRC run can be quickly started, and results viewed for debug using RVE (Results Viewing Environment). Any job customizations can be saved in a runset file for easy re-use in subsequent runs.
Automating Calibre Interface Configurations within Synopsys IC Compiler
Often in your IC design flow you want to trigger events before or after a DRC or LVS run, maybe send an email or run a script to categorize the types of errors and warnings reported. Internal and external triggers are introduced and explained in this video.
Improving Visualization of DRC Errors
Using Virtuoso for IC Layout the error messages from a DRC run can be obscured or hidden underneath polygon layers. The use of a Check Types Overide (CTO) file will help removed un-needed layers making DRC debug easire. To fix a DRC violation a hyperlink to the design rule manual can be created, instead of having to manually look it up.
If you want Calibre to always run multi-threaded and with hyperscale, then you can change your default settings by creating a new defaults file by looking up the variable names. Every project team can decide what their favorite defaults should be, then use a common defaults file.
Saunder Peng shows how to avoid manually documenting a foundry waiver by automating the process in Calibre and creating an HTML report, saving you hours of time.
Instantly Open a Partial Oasis or GDS Database in DESIGNrev
IC layout files greater than 10GB in size can take a huge amount of RAM to load, and involve long wait times. There’s a new option in Calibre called Open Incremental, where you decide the specific area of interest instead of full detail. Just drag your cursor across the area of interest, then you can quickly view DRC errors. About a 10X to 100X speedup in loading is possible using Open Incremental.
Calibre users will save hours to time by learning from each of these how-to videos. The videos are well-edited, take less than 5 minutes, and give you instant time savings. Now that’s a good investment. Mentor has also setup a YouTube channel for IC Nanometer Design where you will find dozens of useful how-to videos.
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