Semiconductor Packaging History and Primer

Semiconductor Packaging History and Primer
by Doug O'Laughlin on 03-09-2022 at 10:00 am

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From DIP to Advanced, semiconductor packaging has become strategic

For ease of reading – I am going to be splitting this primer into two parts. First is the technical overview of everything. Next will be the company-specific writeups that follow over time – specifically Teradyne, Formfactor, Advantest, and Camtek

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eSilicon White Paper on Chiplets – Good Read

eSilicon White Paper on Chiplets – Good Read
by Randy Smith on 10-17-2019 at 10:00 am

eSilicon recently released a paper detailing its experiences and its thoughts on the future of chiplets. The author of the white paper is Dr. Carlos Macián. I have also covered a presentation given by Carlos recently at the AI Hardware Summit, and he is well-spoken and quite knowledgeable. To get the white paper, go to the eSiliconRead More


Fast & Accurate Thermal Analysis of 3D-ICs

Fast & Accurate Thermal Analysis of 3D-ICs
by Pawan Fangaria on 04-14-2014 at 11:00 am

As Moore’s law started saturating on a single semiconductor die, the semiconductor community came up with the approach of growing vertically by stacking dies one above other in a 3D-IC arrangement. However, a major concern with a 3D-IC is that the heat generated by each die can get trapped in the stack, and hence it’s extremely important… Read More


Sketch Router and auto-assist PCB layout

Sketch Router and auto-assist PCB layout
by Don Dingee on 03-31-2014 at 6:30 pm

Archaic tech metaphors abound, stuck in the psyche of users everywhere. We still “dial” numbers, long after the benefit of a short pull area code disappeared. (Humans could dial 1, 2, or 3 a lot faster on a rotary phone, and there were fewer dialpulses for central office switches to decode – thus big cities with more phone traffic like… Read More