UVM: Lowering the barrier to IP reuse

One of my acquaintances at Intel must have some of the same viewing habits I do, based on a recent Tweet he sent. He was probably watching “The Men Who Built America” on the History Channel and thinking as I have a lot recently about how the captains of industry managed to drive ideas to monopolies in the late 1800s and early 1900s.

Difference between 1800’s & today is that barriers to entry r so low & marketplace is so varied that monopolists have very narrow domains.

The comment on technological barriers being lowered is true, especially in a new semiconductor industry that relies more and more on merchant foundries and commercial IP, now the building blocks of choice for most teams. Variation in the market is also a truism, and it is forcing former deathly rivals to cooperate so that all may prosper – a distinct shift in thinking from the winner-take-all thinking that dominated so much of the Industrial Age.

In an EDA industry marked by at least three distinct approaches, the shift in the landscape is driven by a huge problem: IP has only been reusable under carefully controlled conditions, usually meaning adoption of a particular tool chain and verification methodology. Paradoxically, as more IP has been developed, the problem has worsened. Not only does new IP require design and test, but steps are being retraced to reengineer and integrate existing IP into new environments. This mix eventually becomes overwhelming, if not for design resources then certainly for test resources.

The genesis of Universal Verification Methodology (UVM) fascinated a lot of people, wondering why Cadence, Mentor, and Synopsys would cooperate, or even be seen in the same photo. Unifying the disparate approaches to IP verification lowers a major barrier to IP integration and reuse, and UVM provides a better and faster way to test using coverage-driven verification.

More people are getting interested in UVM and SystemVerilog, including participants here at SemiWiki – here are a couple samples of recent forum contributions:

Evolution of the test bench – part 2
SVA : System Verilog Assertion is for Designer too!!

As with any new standard, it takes time for people to understand and embrace the technology. Both the hardware IP designer and the test/verification engineer should take note. The definitive source document is the UVM 1.1 User Guide, free for open download at Accellera.

A new learning resource has debuted this week. Aldec has launched their Fast Track ONLINE training portal, with a series of modules planned on UVM. These self-paced modules give practical examples of concepts related to SystemVerilog, transaction level modeling (TLM), and more on the standard and how to implement it.

Registration is simple, and Fast Track training modules are free.

Creating and leveraging truly reusable IP is one of the keys to getting more designs done, tested, and launched. Success in reusing IP – hardware, software, design, test, everything that goes into the final integrated product – frees up resources for innovative breakthroughs and differentiation of platforms. UVM is a positive change for the EDA industry, and should be a major help for designers willing to embrace it.