Tag: training

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Segmenting the Machine-Learning Hardware Market

Segmenting the Machine-Learning Hardware Market
by Bernard Murphy on 03-13-2019 at 12:00 pm
Categories: AI, Arteris IP, Automotive, FPGA, IoT, IP

One of the great pleasures in what I do is to work with people who are working with people in some of the hottest design areas today. A second-level indirect to be sure but that gives me the luxury of taking a broad view. A recent discussion I had with Kurt Shuler (VP Marketing at Arteris IP) is in this class. As a conscientious marketing… Read More

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Automotive is setting the goalposts for next generation designs

Automotive is setting the goalposts for next generation designs
by Tom Simon on 07-24-2018 at 12:00 pm
Categories: Automotive, EDA, Events, Synopsys

Automotive applications are having a tremendous influence on semiconductor design. This influence is coming from innovations in cloud computing, artificial intelligence, communications, sensors that all serve the requirements of the automotive market. It should come as no surprise that ADAS and autonomous driving are … Read More

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Xilinx, the University of FPGA

Xilinx, the University of FPGA
by Luke Miller on 01-13-2014 at 8:00 pm
Categories: FPGA, Xilinx

More than ever, FPGA training is the key to success. Which is why Xilinx, provides free, no charge video’s that can speak to the seasoned FPGA designer or to the interested community. These Videos are not like your high school graduation taped by Uncle Frank. These are detailed, professionally edited Xilinx Videos that will give… Read More

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Learning Properties, Assertions and Covers for Hardware Design

Learning Properties, Assertions and Covers for Hardware Design
by Daniel Payne on 02-25-2013 at 12:10 pm
Categories: Aldec, EDA

How do you learn new hardware design topics? I just got trained online about property-based verification for hardware designers using a free online class at Aldec. The material was created by Jerry Kaczynski, a Research Engineer at Aldec.

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UVM: Lowering the barrier to IP reuse

UVM: Lowering the barrier to IP reuse
by Don Dingee on 02-06-2013 at 2:00 am
Categories: Aldec, EDA

One of my acquaintances at Intel must have some of the same viewing habits I do, based on a recent Tweet he sent. He was probably watching “The Men Who Built America” on the History Channel and thinking as I have a lot recently about how the captains of industry managed to drive ideas to monopolies in the late 1800s and early 1900s.

Difference

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