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FinFET
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What Comes After FinFET?

What Comes After FinFET?
by Paul McLellan on 08-10-2014 at 11:01 pm
Categories: ESD Alliance, FinFET, Semiconductor Services

So what comes after FinFETs? At 14/16nm (or 22nm if you are Intel) we had FinFET transistors, where the channel was no longer planar but stuck out of the wafer vertically, and the gate wrapped around it on 3 sides. The key thing that made FinFET transistors attractive was that the channel was thin so that the gate controlled it well. … Read More

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Altera vs Xilinx FinFET Update

Altera vs Xilinx FinFET Update
by Daniel Nenni on 07-27-2014 at 10:10 am
Categories: FinFET, FPGA, Xilinx

One of the things I do in my spare time is listen to quarterly conference calls and try to sort fact from fiction. I compare past calls to the current one and attempt to predict what’s coming next. Confucius said, “Study the past if you would define the future” and I’m a big believer in that.

Paul McLellan wrote about the Xilinx call earlier… Read More

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FinFET Based Designs Made Easy & Reliable

FinFET Based Designs Made Easy & Reliable
by Pawan Fangaria on 06-15-2014 at 11:00 am
Categories: Ansys, Inc., EDA, FinFET

Although semiconductor manufacturing has taken off with FinFET based process technology which provides lucrative payoffs on performance improvement, power reduction and area saving in devices for high density and high performance SoC demand of modern era, apprehensions remain about its reliability due to reduced noise … Read More

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Xilinx’s 16nm vs. Altera 14nm

Xilinx’s 16nm vs. Altera 14nm
by Luke Miller on 06-04-2014 at 8:00 pm
Categories: FinFET

You will not believe this, but the family was picking me up Friday evening from the airport and on the way home… Get this, for real, the wife asks me to cut her hair tomorrow. Now the three of you that read my stuff, know what happened before. I resisted, and firmly said ‘No’…The wife seeing my macho stance began appealing to my engineer’s… Read More

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IC Power Noise Reliability for FinFET Designs

IC Power Noise Reliability for FinFET Designs
by Daniel Payne on 05-06-2014 at 9:07 am
Categories: Ansys, Inc., EDA, FinFET

Reliability for ICs is a big deal because the last thing that you want to do is ship a new part only to find out later in the field that there are failures not being caught by testing. I’ve already had two consumer products fail this year because of probable reliability issues: My MacBook Pro with 16GB of RAM started rebooting caused… Read More

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The Infamous Intel FPGA Slide!

The Infamous Intel FPGA Slide!
by Daniel Nenni on 03-11-2014 at 10:30 am
Categories: FinFET, Foundries, FPGA, Intel, TSMC, Xilinx

As I have mentioned before, I’m part of the Coleman Research Group so you can rent me by the hour to better understand the semiconductor industry. Most of the conversations are by phone but sometimes I do travel to the East Coast, Taiwan, Hong Kong, and China for face-to-face meetings. Generally the calls are the result of an event … Read More

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The Alternative to FinFET: FD-SOI

The Alternative to FinFET: FD-SOI
by Paul McLellan on 10-30-2013 at 11:00 am
Categories: FD-SOI, FinFET, Foundries, STMicroelectronics

Everywhere you turn these days you find FinFETs. Intel has had them since 22nm (they use the word Tri-gate but it is the same as what the world calls FinFET) and TSMC will have them at 16nm. So why FinFET? And is there an alternative?

The reason that regular bulk planar transistors have run out of steam is that the channel area underneath… Read More

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Deploying 14nm FinFETs in your Next Mobile SoC

Deploying 14nm FinFETs in your Next Mobile SoC
by Daniel Payne on 06-19-2013 at 11:05 am
Categories: EDA, FinFET, Foundries, GlobalFoundries, Synopsys

At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.

Panelists included:

… Read More
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FinFET Modeling and Extraction at 16-nm

FinFET Modeling and Extraction at 16-nm
by Daniel Payne on 12-18-2012 at 12:05 pm
Categories: EDA, FinFET, Synopsys

In 2012 FinFET is one of the most talked about MOS technologies of the year because traditional planar CMOS has slowed down on scaling below the 28nm node. To learn more about FinFET process modeling I attended a Synopsys webinar where Bari Biswas presented for about 42 minutes include a Q&A portion at the end.


Bari Biswas, Synopsys… Read More

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Introduction to FinFET Technology Part III

Introduction to FinFET Technology Part III
by Tom Dillinger on 11-21-2012 at 5:30 pm
Categories: FinFET, General

The preceding two Semiwiki articles in this thread provided an overview to the FinFET structure and fabrication. The next three articles will discuss some of the unique modeling requirements and design constraints that FinFET’s introduce, compared to planar FET technology.

Due to the complexity of FinFET modeling – … Read More